Raphael Jacquot
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de5bfe83cc
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implement loading into D1 too
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2019-02-09 09:49:22 +01:00 |
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Raphael Jacquot
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8ae31087eb
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bus access all rewritten
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2019-02-09 09:32:29 +01:00 |
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Raphael Jacquot
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c0e4c0b20c
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apply identical treatment for BRAM access
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2019-02-09 01:13:57 +01:00 |
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Raphael Jacquot
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da4299fd19
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reading and writing to the blockram should be in separate always blocks
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2019-02-09 01:06:44 +01:00 |
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Raphael Jacquot
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dfc315937a
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whitespace fix
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2019-02-09 00:59:38 +01:00 |
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Raphael Jacquot
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f8ef195563
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refactor access to the sysram array
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2019-02-09 00:55:09 +01:00 |
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Raphael Jacquot
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229aab83fe
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rename and change a lot of things
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2019-02-09 00:02:09 +01:00 |
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Raphael Jacquot
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686f91f1c9
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Implement reset
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2019-02-09 00:01:48 +01:00 |
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Raphael Jacquot
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c86de581d0
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cleanup
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2019-02-09 00:01:30 +01:00 |
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Raphael Jacquot
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322b176497
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implement RTNSXM, fix RTNCC
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2019-02-09 00:01:18 +01:00 |
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Raphael Jacquot
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ccd373243f
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implement a couple mode opcodes
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2019-02-08 23:59:56 +01:00 |
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Raphael Jacquot
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bb298832ff
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add GOSUB
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2019-02-08 23:59:36 +01:00 |
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Raphael Jacquot
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5a834d9006
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remove
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2019-02-08 21:12:11 +01:00 |
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Raphael Jacquot
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2d5a5d7457
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implement CONFIGURE and DP_WRITE
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2019-02-08 21:11:47 +01:00 |
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Raphael Jacquot
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cd185eeff0
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rewrite in less spaghetti code style
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2019-02-08 19:09:13 +01:00 |
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Raphael Jacquot
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92fe235e07
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add an instruction counter
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2019-02-08 12:46:32 +01:00 |
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Raphael Jacquot
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a56f472a45
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optimize SETDEC
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2019-02-08 11:55:47 +01:00 |
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Raphael Jacquot
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0f456bf0af
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fix more PC handling issues
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2019-02-08 11:47:06 +01:00 |
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Raphael Jacquot
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5559deab1d
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fix more PC stuff
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2019-02-08 11:15:16 +01:00 |
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Raphael Jacquot
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bcf79c9d7d
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fix handling of PC increments and the like
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2019-02-08 11:06:19 +01:00 |
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Raphael Jacquot
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90a8a4e9a9
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implement more stuff
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2019-02-08 00:02:55 +01:00 |
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Raphael Jacquot
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24c49893a1
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implement more instructions, catch errors
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2019-02-07 23:31:35 +01:00 |
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Raphael Jacquot
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55bdfed19a
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entirely redesign the state machine
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2019-02-07 22:54:06 +01:00 |
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Raphael Jacquot
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4800c6f241
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try replacing all ifs with a case... yosys blows up too
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2019-02-07 11:54:11 +01:00 |
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Raphael Jacquot
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0940b198d3
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remove multiple posedge clk, which doesn't work
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2019-02-07 09:38:27 +01:00 |
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Raphael Jacquot
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5a5fc9c775
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fix all bad warnings
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2019-02-07 08:55:41 +01:00 |
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Raphael Jacquot
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b5c3a56273
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separate reading instructions from reading data
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2019-02-07 08:35:59 +01:00 |
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Raphael Jacquot
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b519f3d8b3
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use a yosys config file instead
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2019-02-07 07:11:25 +01:00 |
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Raphael Jacquot
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7a1bc5956e
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add an ifdef
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2019-02-07 07:11:11 +01:00 |
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Raphael Jacquot
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4c9925c1a3
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fix yosys warning
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2019-02-07 07:10:33 +01:00 |
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Raphael Jacquot
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953323c7b8
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rename runstates and starts splitting things up
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2019-02-07 06:29:47 +01:00 |
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Raphael Jacquot
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3c32cbc213
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attempt to fix bus
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2019-02-06 17:50:36 +01:00 |
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Raphael Jacquot
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b8fa3b2df0
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fix nibble_out in bus
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2019-02-06 17:43:14 +01:00 |
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Raphael Jacquot
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62b1ab0292
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attempt at bus are failing. what am I missing ?
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2019-02-06 17:39:25 +01:00 |
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Raphael Jacquot
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b0bbacb0cc
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fix bad assign types
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2019-02-06 16:44:52 +01:00 |
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Raphael Jacquot
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98ff32e61c
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make messages for GOTO, GOVLNG and GOSBVL better
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2019-02-06 16:14:09 +01:00 |
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Raphael Jacquot
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16d9149f1a
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implement the bus, with priority. currently, only rom and io_ram
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2019-02-06 16:04:02 +01:00 |
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Raphael Jacquot
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c77b714777
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implement some of the bus commands for the io_ram module.
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2019-02-06 14:33:44 +01:00 |
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Raphael Jacquot
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82f4df8e93
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add licence info
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2019-02-06 10:40:55 +01:00 |
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Raphael Jacquot
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11d3d1dfef
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add io_ram block (unfinished)
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2019-02-05 08:49:14 +01:00 |
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Raphael Jacquot
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cc632307ea
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implement decoding of data transfers
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2019-02-05 07:07:19 +01:00 |
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Raphael Jacquot
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14272d9978
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finish re-coding all instructions
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2019-02-04 23:51:36 +01:00 |
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Raphael Jacquot
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40d75acc8f
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implement more stuff
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2019-02-04 22:08:17 +01:00 |
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Raphael Jacquot
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713689b0f9
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fix some verilator warnings
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2019-02-04 20:36:47 +01:00 |
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Raphael Jacquot
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355539aaaf
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handle 0
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2019-02-04 18:35:53 +01:00 |
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Raphael Jacquot
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36fb15a209
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add some comments
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2019-02-04 18:17:14 +01:00 |
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Raphael Jacquot
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59186f6bf8
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do more instructions
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2019-02-04 18:00:08 +01:00 |
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Raphael Jacquot
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d743217132
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make it one single process
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2019-02-04 17:46:29 +01:00 |
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Raphael Jacquot
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d2e7f7d035
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commit more stuff
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2019-02-04 17:14:08 +01:00 |
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Raphael Jacquot
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7fcce53689
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implement ST=[01] n
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2019-02-04 17:00:08 +01:00 |
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