alu | ||
.gitignore | ||
compile | ||
dbg_const.v | ||
dbg_module.v | ||
def-alu.v | ||
def-buscmd.v | ||
def-clocks.v | ||
def-fields.v | ||
empty_lfe5u-85f.config | ||
gen_rom_hex.py | ||
gxrom-r-decompile | ||
history.txt | ||
hp48_00_bus.v | ||
hp48_01_io_ram.v | ||
hp48_02_sys_ram.v | ||
hp48_06_rom.v | ||
ico | ||
icoboard.pcf | ||
Makefile | ||
old_bus_controller.v | ||
old_regs.v | ||
README.md | ||
rom-gx-r.hex | ||
run | ||
saturn-core.ESP5.ys | ||
saturn_alu.v | ||
saturn_bus_ctrl.v | ||
saturn_core.ICE40.ys | ||
saturn_core.v | ||
saturn_decoder.v | ||
saturn_decoder_block_8.v | ||
saturn_decoder_block_vars.v | ||
saturn_decoder_debugger.v | ||
saturn_decoder_fields.v | ||
saturn_decoder_registers.v | ||
testrom-2.hex | ||
testrom.hex | ||
text.vcd | ||
ulx3s_v20.lpf |
Verilog implementation of the HP saturn processor
licence: GPLv3 or later
timings:
___________
reset: |____________________________________________________
____ ____ ____ ____ ____ ____
clk : | || || || || || |____
_________ _________ _________ _________ _________
counter: /0____X____1____X____2____X____3____X____0
_________ _________
phase_0: | ||
_________
phase_1: | |____
_________
phase_2: _______________| |
_________
phase_3: ___________________________________| |
notes for using the ULX3S
Maybe linux ujprog won't find port because of insufficient priviledge. Either run ujprog as root or have udev rule:# this is for usb-serial tty device
SUBSYSTEM=="tty", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015",
MODE="664", GROUP="dialout"
this is for ujprog libusb access
ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015",
GROUP="dialout", MODE="666"