mirror of
https://github.com/sxpert/hp-saturn
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307 lines
No EOL
7.6 KiB
Verilog
307 lines
No EOL
7.6 KiB
Verilog
`ifndef _SATURN_DECODER_REGISTERS
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`define _SATURN_DECODER_REGISTERS
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`include "def-alu.v"
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/******************************************************************************
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*
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* set registers from instruction nibble
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*
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*****************************************************************************/
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wire [4:0] reg_ABCD;
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wire [4:0] reg_BCAC;
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wire [4:0] reg_ABAC;
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wire [4:0] reg_BCCD;
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wire [4:0] reg_D0D1;
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wire [4:0] reg_DAT0DAT1;
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wire [4:0] reg_A_C;
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assign reg_ABCD = { 3'b000, i_nibble[1:0]};
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assign reg_BCAC = { 3'b000, i_nibble[0], !(i_nibble[1] || i_nibble[0])};
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assign reg_ABAC = { 3'b000, i_nibble[1] && i_nibble[0], (!i_nibble[1]) && i_nibble[0]};
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assign reg_BCCD = { 3'b000, i_nibble[1] || i_nibble[0], !( i_nibble[1] ^ i_nibble[0])};
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// assign reg_D0D1 = { 4'b0010, (i_nibble[0] && i_nibble[1]) || (i_nibble[2] && i_nibble[3])};
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assign reg_D0D1 = { 4'b0010, i_nibble[0]};
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assign reg_DAT0DAT1 = { 4'b1000, i_nibble[0]};
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assign reg_A_C = { 3'b000, i_nibble[2], 1'b0};
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always @(posedge i_clk) begin
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if (i_reset) begin
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o_reg_dest <= 0;
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o_reg_src1 <= 0;
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o_reg_src2 <= 0;
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inval_opcode_regs <= 0;
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end
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if (do_on_first_nibble) begin
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// reset values on instruction decode start
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case (i_nibble)
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4'h4, 4'h5, 4'h6, 4'h7: begin
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o_reg_dest <= 0;
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o_reg_src1 <= `ALU_REG_IMM;
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o_reg_src2 <= 0;
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end
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default: begin
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o_reg_dest <= 0;
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o_reg_src1 <= 0;
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o_reg_src2 <= 0;
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end
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endcase
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inval_opcode_regs <= 0;
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end
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/************************************************************************
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*
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* set registers for specific instructions
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*
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************************************************************************/
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if (do_block_0x) begin
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case (i_nibble)
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4'h6: begin
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o_reg_dest <= `ALU_REG_RSTK;
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o_reg_src1 <= `ALU_REG_C;
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end
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4'h7: begin
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o_reg_dest <= `ALU_REG_C;
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o_reg_src1 <= `ALU_REG_RSTK;
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end
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4'h8: o_reg_dest <= `ALU_REG_ST;
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4'h9, 4'hB: begin
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o_reg_dest <= `ALU_REG_C;
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o_reg_src1 <= `ALU_REG_ST;
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end
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4'hA: begin
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o_reg_dest <= `ALU_REG_ST;
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o_reg_src1 <= `ALU_REG_C;
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end
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4'hC, 4'hD: begin
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o_reg_dest <= `ALU_REG_P;
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o_reg_src1 <= `ALU_REG_P;
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end
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default: begin
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// inval_opcode_regs <= 1;
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end
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endcase
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end
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if (do_block_0Efx && !in_fields_table) begin
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o_reg_dest <= i_nibble[2]?reg_BCAC:reg_ABCD;
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o_reg_src1 <= i_nibble[2]?reg_BCAC:reg_ABCD;
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o_reg_src2 <= i_nibble[2]?reg_ABCD:reg_BCAC;
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end
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if (do_block_1x) begin
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case (i_nibble)
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4'h6, 4'h8: begin
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o_reg_dest <= `ALU_REG_D0;
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o_reg_src1 <= `ALU_REG_D0;
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end
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4'h7, 4'hC: begin
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o_reg_dest <= `ALU_REG_D1;
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o_reg_src1 <= `ALU_REG_D1;
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end
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4'h9, 4'hA, 4'hB: begin
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o_reg_dest <= `ALU_REG_D0;
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o_reg_src1 <= `ALU_REG_IMM;
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end
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4'hD, 4'hE, 4'hF: begin
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o_reg_dest <= `ALU_REG_D1;
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o_reg_src1 <= `ALU_REG_IMM;
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end
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default: begin end
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endcase
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end
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if (do_block_save_to_R_W) begin
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o_reg_dest <= {2'b01, i_nibble[2:0]};
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o_reg_src1 <= {3'b000, i_nibble[3]?2'b10:2'b00};
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end
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if (do_block_rest_from_R_W || do_block_exch_with_R_W) begin
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o_reg_dest <= {3'b000, i_nibble[3]?2'b10:2'b00};
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o_reg_src1 <= {2'b01, i_nibble[2:0]};
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end
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if (do_block_13x) begin
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o_reg_dest <= i_nibble[1]?reg_A_C:reg_D0D1;
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o_reg_src1 <= i_nibble[2]?`ALU_REG_C:`ALU_REG_A;
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o_reg_src2 <= i_nibble[1]?reg_D0D1:0;
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end
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if (do_block_14x_15xx) begin
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o_reg_dest <= i_nibble[1]?reg_A_C:reg_DAT0DAT1;
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o_reg_src1 <= i_nibble[1]?reg_DAT0DAT1:reg_A_C;
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end
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if (do_block_pointer_arith_const) begin
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o_reg_src2 <= `ALU_REG_IMM;
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end
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if (do_block_2x) begin
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o_reg_dest <= `ALU_REG_P;
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o_reg_src1 <= `ALU_REG_IMM;
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end
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if (do_block_3x) begin
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o_reg_dest <= `ALU_REG_C;
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o_reg_src1 <= `ALU_REG_IMM;
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end
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if (do_block_8x) begin
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case (i_nibble)
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4'h4, 4'h5, 4'h6, 4'h7: begin
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o_reg_dest <= `ALU_REG_ST;
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o_reg_src1 <= `ALU_REG_IMM;
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end
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4'hC, 4'hD, 4'hE, 4'hF: begin
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o_reg_dest <= 0;
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o_reg_src1 <= `ALU_REG_IMM;
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o_reg_src2 <= 0;
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end
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endcase
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end
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if (do_block_80x) begin
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case (i_nibble)
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4'h5: begin
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o_reg_dest <= `ALU_REG_ADDR;
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o_reg_src1 <= `ALU_REG_C;
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o_reg_src2 <= `ALU_REG_NOPE;
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end
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endcase
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end
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if (do_block_80Cx) begin
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o_reg_dest <= `ALU_REG_C;
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o_reg_src1 <= `ALU_REG_P;
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o_reg_src2 <= 0;
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end
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if (do_block_81Af0x) begin
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o_reg_dest <= { 2'b01, i_nibble[2:0]};
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o_reg_src1 <= i_nibble[3]?`ALU_REG_C:`ALU_REG_A;
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o_reg_src2 <= 0;
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end
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if (do_block_81Af1x) begin
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o_reg_dest <= i_nibble[3]?`ALU_REG_C:`ALU_REG_A;
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o_reg_src1 <= { 2'b01, i_nibble[2:0]};
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o_reg_src2 <= 0;
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end
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if (do_block_81Af2x) begin
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o_reg_dest <= i_nibble[3]?`ALU_REG_C:`ALU_REG_A;
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o_reg_src1 <= i_nibble[3]?`ALU_REG_C:`ALU_REG_A;
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o_reg_src2 <= { 2'b01, i_nibble[2:0]};
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end
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if (do_block_82x) begin
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o_reg_dest <= `ALU_REG_HST;
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o_reg_src1 <= `ALU_REG_HST;
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o_reg_src2 <= `ALU_REG_IMM;
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end
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if (do_block_8Ax) begin
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o_reg_dest <= 0;
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o_reg_src1 <= i_nibble[3]?reg_ABCD:reg_BCAC;
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o_reg_src2 <= i_nibble[3]?`ALU_REG_ZERO:reg_ABCD;
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end
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if (do_block_Abx || do_block_Dx) begin
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case ({i_nibble[3],i_nibble[2]})
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2'b00: begin
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o_reg_dest <= reg_ABCD;
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o_reg_src1 <= `ALU_REG_ZERO;
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o_reg_src2 <= 0;
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end
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2'b01: begin
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o_reg_dest <= reg_ABCD;
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o_reg_src1 <= reg_BCAC;
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o_reg_src2 <= 0;
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end
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2'b10: begin
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o_reg_dest <= reg_BCAC;
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o_reg_src1 <= reg_ABCD;
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o_reg_src2 <= 0;
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end
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2'b11: begin // exch
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o_reg_dest <= reg_ABAC;
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o_reg_src1 <= reg_ABAC;
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o_reg_src2 <= reg_BCCD;
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end
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endcase
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end
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if (do_block_Bax) begin
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case ({i_nibble[3],i_nibble[2]})
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2'b00: begin
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o_reg_dest <= reg_ABCD;
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o_reg_src1 <= reg_ABCD;
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o_reg_src2 <= reg_BCAC;
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end
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2'b01: begin
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o_reg_dest <= reg_ABCD;
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o_reg_src1 <= reg_ABCD;
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o_reg_src2 <= 0;
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end
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2'b10: begin
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o_reg_dest <= reg_BCAC;
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o_reg_src1 <= reg_BCAC;
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o_reg_src2 <= reg_ABCD;
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end
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2'b11: begin
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o_reg_dest <= reg_ABCD;
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o_reg_src1 <= reg_BCAC;
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o_reg_src2 <= reg_ABCD;
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end
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endcase
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end
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if (do_block_Bbx) begin
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o_reg_dest <= reg_ABCD;
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o_reg_src1 <= reg_ABCD;
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o_reg_src2 <= 0;
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end
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if (do_block_Cx) begin
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case ({i_nibble[3],i_nibble[2]})
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2'b00: begin
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o_reg_dest <= reg_ABCD;
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o_reg_src1 <= reg_ABCD;
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o_reg_src2 <= reg_BCAC;
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end
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2'b01: begin
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o_reg_dest <= reg_ABCD;
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o_reg_src1 <= reg_ABCD;
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o_reg_src2 <= reg_ABCD;
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end
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2'b10: begin
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o_reg_dest <= reg_BCAC;
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o_reg_src1 <= reg_BCAC;
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o_reg_src2 <= reg_ABCD;
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end
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2'b11: begin // reg = reg - 1
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o_reg_dest <= reg_ABCD;
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o_reg_src1 <= reg_ABCD;
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o_reg_src2 <= 0;
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end
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endcase
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end
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if (do_block_Fx) begin
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case (i_nibble)
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4'h8, 4'h9, 4'hA, 4'hB: begin
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o_reg_dest <= reg_ABCD;
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o_reg_src1 <= reg_ABCD;
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end
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endcase
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o_reg_src2 <= 0;
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end
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end
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`endif |