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99 commits

Author SHA1 Message Date
Raphael Jacquot
570807cf61 time to start over, this this is broken beyond fiddling 2019-02-24 21:54:15 +01:00
Raphael Jacquot
49b20d72f3 restore RTN / RTNCC / RTNSC 2019-02-23 06:57:48 +01:00
Raphael Jacquot
7376c920bc change the clock phase generation from a counter to a shift register 
adapt everywhere needed
 2019-02-22 19:30:53 +01:00
Raphael Jacquot
390bdcd22f simplify things in the ALU 2019-02-22 15:48:11 +01:00
Raphael Jacquot
93d786c2c1 alu rewrite in progress 2019-02-22 08:22:32 +01:00
Raphael Jacquot
93c856666e modify the alu to make it faster for certain operations. 2019-02-21 22:44:55 +01:00
Raphael Jacquot
30d7e6c8df entirely rework the DP_WRITE and WRITE_DP case 2019-02-21 16:55:08 +01:00
Raphael Jacquot
62a1624846 add license 
add some testing stuff, not compelling :-(
 2019-02-20 09:17:37 +01:00
Raphael Jacquot
6bb654944f move the test rom to a separate module 2019-02-19 16:15:03 +01:00
Raphael Jacquot
4cce55e4ba initialize all registers, implement jmp_rel2 
cleanup the controller some more
prepare the core to be rewired
add support for block Bx
 2019-02-18 17:38:25 +01:00
Raphael Jacquot
f660168393 cleanup the simulated rom interface 2019-02-18 11:36:28 +01:00
Raphael Jacquot
1444baca19 implement read from DP 2019-02-18 07:43:36 +01:00
Raphael Jacquot
01429b4493 tested all the way to cycle 400 where transfers from memory need to be fixed in the bus controller 2019-02-17 21:20:18 +01:00
Raphael Jacquot
5c4bff0b5e rewrite the messy hadling of load_dp and dp_write 2019-02-17 20:23:43 +01:00
Raphael Jacquot
0d3c3ecd3e implement CONFIG 
cleanup the bus controller
 2019-02-17 19:29:39 +01:00
Raphael Jacquot
7a3a36bd25 implement the reset bus command 2019-02-17 15:03:36 +01:00
Raphael Jacquot
8fc7cde507 implement the pieces to replicate the bus data transfers for writing data out. 2019-02-17 12:05:38 +01:00
Raphael Jacquot
128921c364 start implementing the bus controller 2019-02-17 08:35:26 +01:00
Raphael Jacquot
500e013bf5 start on the bus controller 2019-02-16 22:38:44 +01:00
Raphael Jacquot
06f79dca88 implemented decoding of 8Ax block, equality and inequality tests over 
field A. needs implementing the actual ALU op
implemented RTNYES/GOYES((not totally finished)
RTNYES works
need to find an actual GOYES to test that
 2019-02-16 11:08:34 +01:00
Raphael Jacquot
ef90d32971 handle block Cx 
add some code to handle goyes / rtnyes after the tests
 2019-02-16 07:35:06 +01:00
Raphael Jacquot
551b618098 fix driver conflicts 2019-02-15 17:23:07 +01:00
Raphael Jacquot
44ca0f4a15 fix driver conflict bug 
implement exch in ALU
fix jump base calculations
correct some things in debugger
fix fields and registers for some instructions
 2019-02-15 16:58:38 +01:00
Raphael Jacquot
25385115e0 separate the decoder in multiple files, it was becoming unwiedly ;-) 2019-02-15 10:47:00 +01:00
Raphael Jacquot
235dbfa913 add some wires 2019-02-15 07:08:11 +01:00
Raphael Jacquot
4b7e59fa21 implement more instructions 2019-02-14 22:14:52 +01:00
Raphael Jacquot
94ab98a175 remove old useless code 
fix some verilator reported bugs
 2019-02-14 15:27:17 +01:00
Raphael Jacquot
bcb44743de add required bits to decode fields tables 2019-02-12 11:22:55 +01:00
Raphael Jacquot
407b0c6d8d implement jump to block_0Ex 2019-02-12 08:48:13 +01:00
Raphael Jacquot
3136a4c37b added tentative decoder stall support 2019-02-12 08:21:32 +01:00
Raphael Jacquot
c7cc7f417b refactor as it was getting too complicated 
secret seems to limit the levels of imbricated ifs...
added
SETHEX
SETDEC
RSTK=C
C=RSTK
 2019-02-12 07:48:25 +01:00
Raphael Jacquot
d4c67cf8fc finally, something that is synthesizable ! 2019-02-12 00:07:12 +01:00
Raphael Jacquot
9ecdc1799b successfully handles the first 4 opcodes and bails out on error 2019-02-11 22:57:00 +01:00
Raphael Jacquot
17c2278c99 yay, decodes the first 4 opcodes \o/ 2019-02-11 22:29:13 +01:00
Raphael Jacquot
c454fb8b97 test of new decoder structure 2019-02-11 21:29:04 +01:00
Raphael Jacquot
2c06ce0359 major surgery in progress 2019-02-11 20:27:51 +01:00
Raphael Jacquot
9b2f5fa41c more clocking work 2019-02-11 19:49:22 +01:00
Raphael Jacquot
be83ee0eed rework the clocking 2019-02-11 19:24:57 +01:00
Raphael Jacquot
cbfbe4eb3f renumber debug opcodes 
add add_cst and sub_cst alu opcodes
port pointer math to use ALU
make A[ab]x more readable
 2019-02-11 15:36:51 +01:00
Raphael Jacquot
9799ea7618 use the ALU for 13x opcodes 
comment debug code
add some debug code elsewhere
 2019-02-11 13:17:18 +01:00
Raphael Jacquot
b39c56a43c make things more readable 2019-02-11 11:29:31 +01:00
Raphael Jacquot
6d8924cf1d clear alu_debug and dbg_op_code on each instruction start 2019-02-11 10:29:05 +01:00
Raphael Jacquot
046fa457be add stuff for a future debugger 2019-02-11 09:13:16 +01:00
Raphael Jacquot
46890c6394 refactor ALU operations 2019-02-11 07:04:42 +01:00
Raphael Jacquot
d6b59740dd add Dn=(2) 2019-02-10 23:00:20 +01:00
Raphael Jacquot
799fc3c327 convert stuff to use the ALU module instead 2019-02-10 22:02:39 +01:00
Raphael Jacquot
f21dcd8c23 add alu stuff 2019-02-10 18:46:26 +01:00
Raphael Jacquot
4e33d9c145 fix documentation comprehension error 2019-02-10 13:50:11 +01:00
Raphael Jacquot
efd93e4a95 add or substract constant do D0 and D1 2019-02-10 13:39:56 +01:00
Raphael Jacquot
bde3e1a027 add D0=(4) and transfer on field W 2019-02-10 12:47:50 +01:00