Miroirs/hp-saturn
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24 commits

Author SHA1 Message Date
Raphael Jacquot
570807cf61 time to start over, this this is broken beyond fiddling 2019-02-24 21:54:15 +01:00
Raphael Jacquot
49b20d72f3 restore RTN / RTNCC / RTNSC 2019-02-23 06:57:48 +01:00
Raphael Jacquot
7376c920bc change the clock phase generation from a counter to a shift register 
adapt everywhere needed
 2019-02-22 19:30:53 +01:00
Raphael Jacquot
2028715939 implement PC related functionnality, relative and absolute jumps 2019-02-22 12:00:23 +01:00
Raphael Jacquot
93d786c2c1 alu rewrite in progress 2019-02-22 08:22:32 +01:00
Raphael Jacquot
93c856666e modify the alu to make it faster for certain operations. 2019-02-21 22:44:55 +01:00
Raphael Jacquot
7e6250f59b fix off-by-one error in write loop 2019-02-21 17:10:03 +01:00
Raphael Jacquot
30d7e6c8df entirely rework the DP_WRITE and WRITE_DP case 2019-02-21 16:55:08 +01:00
Raphael Jacquot
7d63f0f57a cleanups and move things around 2019-02-20 17:36:21 +01:00
Raphael Jacquot
70ddc7f9b6 cleanups of the bus controller (more to do) 2019-02-20 16:21:39 +01:00
Raphael Jacquot
ec9c39150d start rewriting logical equations to make them cleaner 
(oh my this is hard)
 2019-02-20 09:20:16 +01:00
Raphael Jacquot
380ef1a425 complete rewrite 2019-02-19 16:17:35 +01:00
Raphael Jacquot
4cce55e4ba initialize all registers, implement jmp_rel2 
cleanup the controller some more
prepare the core to be rewired
add support for block Bx
 2019-02-18 17:38:25 +01:00
Raphael Jacquot
f660168393 cleanup the simulated rom interface 2019-02-18 11:36:28 +01:00
Raphael Jacquot
1444baca19 implement read from DP 2019-02-18 07:43:36 +01:00
Raphael Jacquot
0a45b014d7 moved main registers to arrays, makes things much simpler and better, it seems 2019-02-17 23:05:33 +01:00
Raphael Jacquot
01429b4493 tested all the way to cycle 400 where transfers from memory need to be fixed in the bus controller 2019-02-17 21:20:18 +01:00
Raphael Jacquot
5c4bff0b5e rewrite the messy hadling of load_dp and dp_write 2019-02-17 20:23:43 +01:00
Raphael Jacquot
0d3c3ecd3e implement CONFIG 
cleanup the bus controller
 2019-02-17 19:29:39 +01:00
Raphael Jacquot
7a3a36bd25 implement the reset bus command 2019-02-17 15:03:36 +01:00
Raphael Jacquot
1c719a1828 cleanup and reorganization for readability 2019-02-17 12:57:38 +01:00
Raphael Jacquot
8fc7cde507 implement the pieces to replicate the bus data transfers for writing data out. 2019-02-17 12:05:38 +01:00
Raphael Jacquot
128921c364 start implementing the bus controller 2019-02-17 08:35:26 +01:00
Raphael Jacquot
500e013bf5 start on the bus controller 2019-02-16 22:38:44 +01:00