mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-29 10:23:22 +01:00
168 lines
No EOL
3.3 KiB
Verilog
168 lines
No EOL
3.3 KiB
Verilog
`ifndef _SATURN_BUS_CTRL
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`define _SATURN_BUS_CTRL
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`include "def-clocks.v"
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`include "def-buscmd.v"
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module saturn_bus_ctrl (
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// basic stuff
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i_clk,
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i_reset,
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i_cycle_ctr,
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i_en_bus_send,
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i_en_bus_recv,
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i_en_bus_ecmd,
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i_stalled,
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i_read_stall,
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o_stalled_by_bus,
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// bus i/o
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i_bus_data,
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o_bus_data,
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o_bus_strobe,
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o_bus_cmd_data,
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// interface to the rest of the machine
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i_alu_pc,
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i_address,
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i_load_pc,
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i_load_dp,
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i_nibble,
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o_nibble
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_reset;
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input wire [31:0] i_cycle_ctr;
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input wire [0:0] i_en_bus_send;
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input wire [0:0] i_en_bus_recv;
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input wire [0:0] i_en_bus_ecmd;
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input wire [0:0] i_stalled;
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input wire [0:0] i_read_stall;
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output reg [0:0] o_stalled_by_bus;
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input wire [3:0] i_bus_data;
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output reg [3:0] o_bus_data;
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output reg [0:0] o_bus_strobe;
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output reg [0:0] o_bus_cmd_data;
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input wire [19:0] i_alu_pc;
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input wire [19:0] i_address;
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input wire [0:0] i_load_pc;
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input wire [0:0] i_load_dp;
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input wire [3:0] i_nibble;
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output reg [3:0] o_nibble;
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/*
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* events
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*/
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wire en_bus_send;
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assign en_bus_send = i_en_bus_send && !i_stalled;
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wire en_bus_recv;
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assign en_bus_recv = i_en_bus_recv && !i_stalled;
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wire en_bus_ecmd;
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assign en_bus_ecmd = i_en_bus_ecmd && !i_stalled;
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/*
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* test rom...
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*/
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`ifdef SIM
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`define ROMBITS 20
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`else
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`define ROMBITS 10
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`endif
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reg [3:0] rom [0:2**`ROMBITS-1];
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initial begin
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`ifdef SIM
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$readmemh("rom-gx-r.hex", rom);
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// $readmemh( "testrom-2.hex", rom);
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// $monitor("addr %5h | strb %b | c/d %b | cnt %0d | odata %h | idata %h",
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// i_address, o_bus_strobe, o_bus_cmd_data, addr_cnt, o_bus_data, i_bus_data);
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`endif
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end
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reg [2:0] addr_cnt;
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reg [0:0] send_addr;
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reg [19:0] local_pc;
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always @(posedge i_clk) begin
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if (i_reset) begin
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o_stalled_by_bus <= 0;
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o_bus_strobe <= 0;
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o_bus_cmd_data <= 1; // 1 is the default level
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addr_cnt <= 0;
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end
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/*
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*
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* sending commands or data to the bus
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*
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*/
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if (en_bus_send) begin
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if (i_load_pc) begin
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$display("BUS_SEND %0d: loading pc %h", `PH_BUS_SEND, i_address);
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o_bus_data <= `BUSCMD_LOAD_PC;
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end
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if (i_load_dp) begin
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$display("BUS_SEND %0d: loading dp %h", `PH_BUS_SEND, i_address);
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o_bus_data <= `BUSCMD_LOAD_DP;
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end
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if (i_load_pc || i_load_dp) begin
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o_stalled_by_bus <= 1;
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o_bus_cmd_data <= 0;
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addr_cnt <= 0;
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send_addr <= 1;
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end
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if (send_addr) begin
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$display("BUS_SEND %0d: send addr nibble %0d [%h]", `PH_BUS_SEND, addr_cnt, i_address[addr_cnt*4+:4]);
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o_bus_data <= i_address[addr_cnt*4+:4];
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addr_cnt <= addr_cnt + 1;
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end
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if (!i_read_stall || send_addr)
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o_bus_strobe <= 1;
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end
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if (en_bus_ecmd && send_addr && (addr_cnt == 5)) begin
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$display("BUS_ECMD %0d: releasing stall after sending addr", `PH_BUS_ECMD);
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send_addr <= 0;
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o_stalled_by_bus = 0;
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end
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/*
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*
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* reading data from the bus
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*
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*/
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if (en_bus_recv && !i_read_stall) begin
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$display("BUS_RECV %0d: [%d] nibble %h", `PH_BUS_RECV, i_cycle_ctr, rom[i_alu_pc[`ROMBITS-1:0]]);
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o_nibble <= rom[i_alu_pc[`ROMBITS-1:0]];
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end
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/*
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*
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* resets the bus automatically
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*
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*/
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if (en_bus_recv) begin
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o_bus_strobe <= 0;
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o_bus_cmd_data <= 1;
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end
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end
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endmodule
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`endif |