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Author	SHA1	Message	Date
Matthew Berry	adeb05911b	thumb high reg bx ops only set flags on cmp	2020-10-29 00:10:20 -07:00
Matthew Berry	fa5746cc0b	update bitfield version to get field locking support	2020-10-28 00:01:04 -07:00
Matthew Berry	4cc36e2bf6	data procesing move spsr to cpsr if rd == r15	2020-10-26 00:03:20 -07:00
Matthew Berry	723f3a6661	special rrx case	2020-10-25 18:01:00 -07:00
Matthew Berry	8538a0445a	properly handle rotating registers by an immediate, asr0=asr32	2020-10-25 14:07:00 -07:00
Matthew Berry	bfc53e0222	handle difference between lsr immediates/registers, pass imm flag to all shifts	2020-10-25 00:48:45 -07:00
Matthew Berry	5749cd3a24	abstract register writing (always align and clear pipeline on pc writes)	2020-10-24 16:00:12 -07:00
Matthew Berry	2188e81c5b	add oam, pram read mirroring	2020-10-24 13:41:23 -07:00
Matthew Berry	5a298dd41c	fix sbc carry flag	2020-10-24 11:33:04 -07:00
Matthew Berry	c589e8f6ef	fix thumb long branch link weird sign logic	2020-10-24 01:22:03 -07:00
Matthew Berry	a5ebfd603c	fix thumb high reg branch exchange: don't write on cmp	2020-10-23 23:29:05 -07:00
Matthew Berry	bef0d366b6	don't bank cpsr, fix cpsr->spsr copy, make mode enum return u32	2020-10-23 23:27:34 -07:00
Matthew Berry	1f9fad7777	set conditions flag on shift imm	2020-10-23 23:25:18 -07:00
Matthew Berry	94a063adc3	clear pipeline in block data transfer when writing to pc	2020-10-23 00:03:24 -07:00
Matthew Berry	476bb6afd4	only print to console if rendering in unsupported bg mode	2020-10-22 23:53:30 -07:00
Matthew Berry	7b34b5696b	add spsr, fix psr transfer (switch mode), set sp on boot, default ppu mode 3	2020-10-22 23:05:49 -07:00
Matthew Berry	2a43b20797	bump bitfield version, add post_init to force all components to init at start	2020-10-21 22:19:32 -07:00
Matthew Berry	da624104fd	support adding bios (necessary for interrupts)	2020-10-20 08:25:26 -07:00
Matthew Berry	b401524ea5	arm / thumb software interrupts, register banking	2020-10-19 00:00:05 -07:00
Matthew Berry	49f6d39e84	ror edge-case if bits&31==0	2020-10-18 17:13:51 -07:00
Matthew Berry	71d714fcab	adc properly handle case when op2=0xFFFFFFFF and carry is set	2020-10-18 12:33:22 -07:00
Matthew Berry	2ea0eda602	asr handle case where shift > 31	2020-10-18 12:15:46 -07:00
Matthew Berry	860fc64b11	ror &= 31	2020-10-18 11:53:30 -07:00
Matthew Berry	e64b17aea4	asr simply return the word if the shift is 0	2020-10-18 11:38:56 -07:00
Matthew Berry	c6a1db4f6c	lsr simply return the word if the shift is 0	2020-10-18 11:27:59 -07:00
Matthew Berry	5db41fa7b2	write to console on unaligned reads instead of aborting	2020-10-18 01:09:28 -07:00
Matthew Berry	7a4680cf8e	arm halfword data transfer register offset	2020-10-18 00:29:36 -07:00
Matthew Berry	a10079c1d5	arm single data swap	2020-10-17 23:58:24 -07:00
Matthew Berry	cce814a3a7	fix signed long multiply and negative flag	2020-10-17 11:18:22 -07:00
Matthew Berry	b51e07b643	keyinput implemented	2020-10-17 00:18:11 -07:00
Matthew Berry	337e7d0bc8	render mode 4 w/ page flipping, stub green swap	2020-10-15 23:47:58 -07:00
Matthew Berry	e1f348ac1c	barrel shifter handle rotation of 0 bits	2020-10-14 00:00:01 -07:00
Matthew Berry	0f0d2a4c20	arm data processing clear pipeline if r15=rd	2020-10-13 23:15:29 -07:00
Matthew Berry	025a0c3d5b	stub keypad to 0xFF (no keys pressed)	2020-10-13 23:14:17 -07:00
Matthew Berry	cbe206b13e	implement sbc, make data_processing use abstracted arith	2020-10-13 18:59:40 -07:00
Matthew Berry	86195d55d1	arm multiply long	2020-10-12 00:10:44 -07:00
Matthew Berry	54dcc01487	allow multiplication wrapping	2020-10-11 23:56:56 -07:00
Matthew Berry	3d0408d702	set proper flags for adc	2020-10-11 23:47:21 -07:00
Matthew Berry	ad446281fc	fix stmia register order	2020-10-11 20:07:28 -07:00
Matthew Berry	155f0a7f68	arm single data transfer respect byte quantity	2020-10-11 19:56:53 -07:00
Matthew Berry	4654d15e2a	arm fix strh, only store halfword	2020-10-11 19:44:31 -07:00
Matthew Berry	f9c8ae7668	thumb load address	2020-10-11 13:33:04 -07:00
Matthew Berry	e8de35e27e	fix large asr	2020-10-11 13:32:35 -07:00
Matthew Berry	403bd71d7e	impl bgcnt registers	2020-10-11 12:23:13 -07:00
Matthew Berry	367b578d9f	clear pipeline if rd==15 in thumb hi-reg bx, load/store imm, load/store reg	2020-10-11 10:29:22 -07:00
Matthew Berry	b52599ae2d	thumb fix conditional branch crash on wrong int type	2020-10-10 20:38:48 -07:00
Matthew Berry	9b1f73e741	thumb load/store register offset	2020-10-10 20:38:15 -07:00
Matthew Berry	dfb833a351	arm multiply, fix arm lut bit selection	2020-10-10 18:48:08 -07:00
Matthew Berry	4a2f0a6789	scheduler, ppu vcount/dispstat on scheduler, ppu io fix read/write order	2020-10-09 21:01:04 -07:00
Matthew Berry	71235e4b2a	arm fix negative branch offset	2020-10-09 20:17:51 -07:00