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arm multiply, fix arm lut bit selection

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Matthew Berry 2020-10-10 18:48:08 -07:00
parent 4a2f0a6789
commit dfb833a351
2 changed files with 22 additions and 6 deletions
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11
src/crab/arm/arm.cr
View file

@ -36,11 +36,6 @@ module ARM
# undefined
elsif idx & 0b110000000000 == 0b010000000000
lut[idx] = ->arm_single_data_transfer(Word)
elsif idx & 0b111001001001 == 0b000001001001
# halfword data transfer immediate offset
lut[idx] = ->arm_halfword_data_transfer_immediate(Word)
elsif idx & 0b111001001001 == 0b000000001001
# halfword data transfer register offset
elsif idx & 0b111111111111 == 0b000100100001
lut[idx] = ->arm_branch_exchange(Word)
elsif idx & 0b111110111111 == 0b000100001001
@ -48,7 +43,11 @@ module ARM
elsif idx & 0b111110001111 == 0b000010001001
# multiply long
elsif idx & 0b111111001111 == 0b000000001001
# multiply
lut[idx] = ->arm_multiply(Word)
elsif idx & 0b111001001001 == 0b000001001001
lut[idx] = ->arm_halfword_data_transfer_immediate(Word)
elsif idx & 0b111001001001 == 0b000000001001
# halfword data transfer register offset
elsif idx & 0b110110010000 == 0b000100000000
lut[idx] = ->arm_psr_transfer(Word)
elsif idx & 0b110000000000 == 0b000000000000

17
src/crab/arm/multiply.cr Normal file
View file

@ -0,0 +1,17 @@
module ARM
def arm_multiply(instr : Word) : Nil
accumulate = bit?(instr, 21)
set_conditions = bit?(instr, 20)
rd = bits(instr, 16..19)
rn = bits(instr, 12..15)
rs = bits(instr, 8..11)
rm = bits(instr, 0..3)
@r[rd] = @r[rm] * @r[rs]
@r[rd] &+= @r[rn] if accumulate
if set_conditions
@cpsr.zero = @r[rd] == 0
@cpsr.negative = bit?(@r[rd], 31)
end
end
end