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arm data processing clear pipeline if r15=rd

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Matthew Berry 2020-10-13 23:15:29 -07:00
parent 025a0c3d5b
commit 0f0d2a4c20
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src/crab/arm/data_processing.cr
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@ -34,5 +34,6 @@ module ARM
@cpsr.zero = res == 0
@cpsr.negative = bit?(res, 31)
end
clear_pipeline if rd == 15 # todo only do this when needed (not 0xA or 0xB)
end
end