From 0f0d2a4c20452640fa5f5ad5ba2910aa471c5aa0 Mon Sep 17 00:00:00 2001 From: Matthew Berry Date: Tue, 13 Oct 2020 23:15:29 -0700 Subject: [PATCH] arm data processing clear pipeline if r15=rd --- src/crab/arm/data_processing.cr | 1 + 1 file changed, 1 insertion(+) diff --git a/src/crab/arm/data_processing.cr b/src/crab/arm/data_processing.cr index 792f20d..8d1c889 100644 --- a/src/crab/arm/data_processing.cr +++ b/src/crab/arm/data_processing.cr @@ -34,5 +34,6 @@ module ARM @cpsr.zero = res == 0 @cpsr.negative = bit?(res, 31) end + clear_pipeline if rd == 15 # todo only do this when needed (not 0xA or 0xB) end end