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clear pipeline if rd==15 in thumb hi-reg bx, load/store imm, load/store reg

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Matthew Berry 2020-10-11 10:29:22 -07:00
parent b52599ae2d
commit 367b578d9f
3 changed files with 26 additions and 17 deletions
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1
src/crab/thumb/hi_reg_branch_exchange.cr
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@ -22,5 +22,6 @@ module THUMB
end
clear_pipeline
end
clear_pipeline if rd == 15
end
end

13
src/crab/thumb/load_store_immediate_offset.cr
View file

@ -5,11 +5,16 @@ module THUMB
rb = bits(instr, 3..5)
rd = bits(instr, 0..2)
imm = offset << 2
address = @r[rb] &+ (offset << 2)
case byte_quantity_and_load
when 0b00 then @gba.bus[@r[rb] + imm] = @r[rd]
when 0b01 then @r[rd] = @gba.bus.read_word(@r[rb] + imm)
when 0b10 then @gba.bus[@r[rb] + imm] = @r[rd].to_u8!
when 0b11 then @r[rd] = @gba.bus[@r[rb] + imm].to_u32
when 0b00 then @gba.bus[address] = @r[rd]
when 0b01
@r[rd] = @gba.bus.read_word(address)
clear_pipeline if rd == 15
when 0b10 then @gba.bus[address] = 0xFF_u8 & @r[rd]
when 0b11
@r[rd] = 0xFFFFFFFF_u32 & @gba.bus[address]
clear_pipeline if rd == 15
end
end
end

29
src/crab/thumb/load_store_register_offset.cr
View file

@ -1,16 +1,19 @@
module THUMB
def thumb_load_store_register_offset(instr : Word) : Nil
load_and_byte_quantity = bits(instr, 10..11)
ro = bits(instr, 6..8)
rb = bits(instr, 3..5)
rd = bits(instr, 0..2)
address = @r[rb] &+ @r[ro]
case load_and_byte_quantity
when 0b00 then @gba.bus[address] = @r[rd]
when 0b01 then @gba.bus[address] = 0xFF_u8 & @r[rd]
when 0b10 then @r[rd] = @gba.bus.read_word address
when 0b11 then @r[rd] = 0xFFFFFFFF_u32 & @gba.bus[address]
end
def thumb_load_store_register_offset(instr : Word) : Nil
load_and_byte_quantity = bits(instr, 10..11)
ro = bits(instr, 6..8)
rb = bits(instr, 3..5)
rd = bits(instr, 0..2)
address = @r[rb] &+ @r[ro]
case load_and_byte_quantity
when 0b00 then @gba.bus[address] = @r[rd]
when 0b01 then @gba.bus[address] = 0xFF_u8 & @r[rd]
when 0b10
@r[rd] = @gba.bus.read_word address
clear_pipeline if rd == 15
when 0b11
@r[rd] = 0xFFFFFFFF_u32 & @gba.bus[address]
clear_pipeline if rd == 15
end
end
end