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implement sbc, make data_processing use abstracted arith
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3 changed files with 18 additions and 5 deletions
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@ -17,9 +17,9 @@ module ARM
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when 0x2 then res = @r[rd] = sub(@r[rn], operand_2, set_conditions)
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when 0x3 then res = @r[rd] = sub(operand_2, @r[rn], set_conditions)
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when 0x4 then res = @r[rd] = add(@r[rn], operand_2, set_conditions)
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when 0x5 then res = @r[rd] = @r[rn] &+ operand_2 &+ @cpsr.carry.to_unsafe
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when 0x6 then res = @r[rd] = @r[rn] &- operand_2 &+ @cpsr.carry.to_unsafe &- 1
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when 0x7 then res = @r[rd] = operand_2 &- @r[rn] &+ @cpsr.carry.to_unsafe &- 1
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when 0x5 then res = @r[rd] = adc(@r[rn], operand_2, set_conditions)
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when 0x6 then res = @r[rd] = sbc(@r[rn], operand_2, set_conditions)
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when 0x7 then res = @r[rd] = sbc(operand_2, @r[rn], set_conditions)
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when 0x8 then res = @r[rn] & operand_2
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when 0x9 then res = @r[rn] ^ operand_2
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when 0xA then res = sub(@r[rn], operand_2, set_conditions)
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@ -125,6 +125,19 @@ class CPU
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res
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end
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# Subtract two values with carry
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def sbc(operand_1 : Word, operand_2 : Word, set_conditions) : Word
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log "sbc - operand_1:#{hex_str operand_1}, operand_2:#{hex_str operand_2}"
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res = operand_1 &- operand_2 &+ @cpsr.carry.to_unsafe &- 1
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if set_conditions
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@cpsr.overflow = bit?((operand_1 ^ operand_2) & (operand_1 ^ res), 31)
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@cpsr.carry = operand_1 >= operand_2
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@cpsr.zero = res == 0
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@cpsr.negative = bit?(res, 31)
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end
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res
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end
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# Add two values
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def add(operand_1 : Word, operand_2 : Word, set_conditions) : Word
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log "add - operand_1:#{hex_str operand_1}, operand_2:#{hex_str operand_2}"
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@ -11,14 +11,14 @@ module THUMB
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when 0b0011 then res = @r[rd] = lsr(@r[rd], @r[rs], true)
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when 0b0100 then res = @r[rd] = asr(@r[rd], @r[rs], true)
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when 0b0101 then res = @r[rd] = adc(@r[rd], @r[rs], true)
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when 0b0110 then res = @r[rd] = @r[rd] &- @r[rs] &- ~@cpsr.carry.to_unsafe
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when 0b0110 then res = @r[rd] = sbc(@r[rd], @r[rs], true)
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when 0b0111 then res = @r[rd] = ror(@r[rd], @r[rs], true)
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when 0b1000 then res = @r[rd] & @r[rs]
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when 0b1001 then res = @r[rd] = (-@r[rs].to_i32!).to_u32!
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when 0b1010 then res = sub(@r[rd], @r[rs], true)
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when 0b1011 then res = add(@r[rd], @r[rs], true)
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when 0b1100 then res = @r[rd] = @r[rd] | @r[rs]
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when 0b1101 then res = @r[rd] = @r[rs] * @r[rd]
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when 0b1101 then res = @r[rd] = @r[rs] &* @r[rd]
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when 0b1110 then res = @r[rd] = @r[rd] & ~@r[rs]
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when 0b1111 then res = @r[rd] = ~@r[rs]
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else raise "Invalid alu op: #{op}"
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