fix stmia register order

src/crab/arm/block_data_transfer.cr

@@ -19,7 +19,7 @@ module ARM
         end
       end
     else
-      16.times do |idx|
+      15.downto(0).each do |idx|
         if bit?(list, idx)
           address &+= add ? 4 : -4 if pre_index
           @gba.bus[address] = @r[idx]

src/crab/thumb/multiple_load_store.cr

@@ -12,7 +12,7 @@ module THUMB
         end
       end
     else # stmia
-      8.times do |idx|
+      7.downto(0).each do |idx|
         if bit?(list, idx)
           @gba.bus[address] = @r[idx]
           address &+= 4