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2019-02-19 16:16:18 +01:00
alu rework the clocking 2019-02-11 19:24:57 +01:00
.gitignore major changes in the fields decoder 2019-02-12 21:43:54 +01:00
compile add testing for yosys out status 2019-02-12 14:50:13 +01:00
dbg_const.v renumber debug opcodes 2019-02-11 15:36:51 +01:00
dbg_module.v add stuff for a future debugger 2019-02-11 09:13:16 +01:00
def-alu.v implement CONFIG 2019-02-17 19:29:39 +01:00
def-buscmd.v start on the bus controller 2019-02-16 22:38:44 +01:00
def-clocks.v start implementing the bus controller 2019-02-17 08:35:26 +01:00
def-fields.v start handling ALU related stuff 2019-02-12 12:43:36 +01:00
empty_lfe5u-85f.config fix some verilator warnings 2019-02-04 20:36:47 +01:00
gen_rom_hex.py add licence info 2019-02-06 10:40:55 +01:00
gxrom-r-decompile implement ST=[01] n 2019-02-04 17:00:08 +01:00
history.txt save one cycle on P= n 2019-02-18 11:36:39 +01:00
hp48_00_bus.v bus access all rewritten 2019-02-09 09:32:29 +01:00
hp48_01_io_ram.v add more stuff 2019-02-09 11:53:45 +01:00
hp48_02_sys_ram.v implement more things, test with ice40 2019-02-10 12:04:53 +01:00
hp48_06_rom.v implement more things, test with ice40 2019-02-10 12:04:53 +01:00
ico implement more things, test with ice40 2019-02-10 12:04:53 +01:00
icoboard.pcf implement more things, test with ice40 2019-02-10 12:04:53 +01:00
Makefile implement ST=[01] n 2019-02-04 17:00:08 +01:00
old_bus_controller.v major surgery in progress 2019-02-11 20:27:51 +01:00
old_regs.v major surgery in progress 2019-02-11 20:27:51 +01:00
README.md cleanup the simulated rom interface 2019-02-18 11:36:28 +01:00
rom-gx-r.hex change the way the rom is encoded, makes things easier 2019-02-04 11:31:58 +01:00
run remove old useless code 2019-02-14 15:27:17 +01:00
saturn-core.ESP5.ys implement more instructions 2019-02-14 22:14:52 +01:00
saturn_alu.v initialize all registers, implement jmp_rel2 2019-02-18 17:38:25 +01:00
saturn_bus_ctrl.v initialize all registers, implement jmp_rel2 2019-02-18 17:38:25 +01:00
saturn_core.ICE40.ys implement more things, test with ice40 2019-02-10 12:04:53 +01:00
saturn_core.v move the test rom to a separate module 2019-02-19 16:15:03 +01:00
saturn_decoder.v initialize all registers, implement jmp_rel2 2019-02-18 17:38:25 +01:00
saturn_decoder_block_8.v add more instructions 2019-02-19 16:16:00 +01:00
saturn_decoder_block_vars.v initialize all registers, implement jmp_rel2 2019-02-18 17:38:25 +01:00
saturn_decoder_debugger.v support some more jump instructions 2019-02-19 16:16:18 +01:00
saturn_decoder_fields.v add some instructions and debug 2019-02-19 16:15:46 +01:00
saturn_decoder_registers.v add some instructions and debug 2019-02-19 16:15:46 +01:00
testrom-2.hex initialize all registers, implement jmp_rel2 2019-02-18 17:38:25 +01:00
testrom.hex finished blocks 1, 2 and 3 2019-02-13 20:09:25 +01:00
text.vcd implement ST=[01] n 2019-02-04 17:00:08 +01:00
ulx3s_v20.lpf commit more stuff 2019-02-04 17:14:08 +01:00

Verilog implementation of the HP saturn processor

licence: GPLv3 or later

timings: ___________
reset: |____________________________________________________ ____ ____ ____ ____ ____ ____ clk : | || || || || || |____ _________ _________ _________ _________ _________ counter: /0____X____1____X____2____X____3____X____0 _________ _________ phase_0: | || _________ phase_1: | |____ _________ phase_2: _______________| | _________ phase_3: ___________________________________| |

notes for using the ULX3S

Maybe linux ujprog won't find port because of insufficient priviledge. Either run ujprog as root or have udev rule:# this is for usb-serial tty device SUBSYSTEM=="tty", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015",
MODE="664", GROUP="dialout" this is for ujprog libusb access

ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6015",
GROUP="dialout", MODE="666"