12 commits

Author	SHA1	Message	Date
Raphaël Jacquot	009f01f5d7	implement 8[45]x ST=[01] n ... implement GOVLNG dump 2 lines of registers in debugger now	2019-03-04 08:08:02 +01:00
Raphaël Jacquot	6dd38500a8	add a counter to slow things down	2019-03-03 15:19:07 +01:00
Raphaël Jacquot	b58be38b10	connect debugger to leds	2019-03-03 13:33:32 +01:00
Raphaël Jacquot	eeb5150159	add the beginnings of a PC and RSTK handler ... fix bad maths in the rom-gx-r module wire in the PC in the debugger and the control unit add an execute flag, to start execution of partially decoded instructions that need reading data from the instruction stream	2019-03-03 09:33:42 +01:00
Raphael Jacquot	21ad359673	fix compiling ... fix the way the bus controller program worked, which generated evil inferred latches	2019-03-02 22:33:58 +01:00
Raphaël Jacquot	2fcd9f7b23	decode our first instruction ... execute said instruction start implementing the debugging engine to see what we are doing	2019-03-02 19:40:31 +01:00
Raphael Jacquot	c5355b4a90	enough was done to start feeding the decoder	2019-03-02 15:52:56 +01:00
Raphael Jacquot	cd2b74dcc8	add some commenting	2019-03-02 15:01:00 +01:00
Raphael Jacquot	3cbd6ac5e1	we are now up to reading the first instruction nibbles	2019-03-02 14:38:01 +01:00
Raphael Jacquot	8ce2d2a993	implement more of the bus controller	2019-03-02 13:22:09 +01:00
Raphael Jacquot	e761f984c8	implement the basic rom, and add a few things	2019-02-25 09:17:17 +01:00
Raphael Jacquot	8866b8c175	starts complete rewrite	2019-02-24 23:30:57 +01:00