10 commits

Author	SHA1	Message	Date
Raphael Jacquot	a533e4ea37	cleanup the startup procedure	2019-03-14 17:52:03 +01:00
Raphael Jacquot	c62d562008	make it so that execution of bus programs happen ... in the same cycle as the instruction modify the way jump and rtn are handled add some registers to the debugger	2019-03-14 16:37:51 +01:00
Raphaël Jacquot	f86a1d03c5	implement base alu functionnality	2019-03-06 12:16:34 +01:00
Raphaël Jacquot	28483afe9a	implement CONFIG and RTN* (0[0-3])	2019-03-05 05:39:34 +01:00
Raphaël Jacquot	479382e004	export rstk_ptr to debugger ... implement LCHEX (and almost done for LAHEX)	2019-03-04 13:28:08 +01:00
Raphaël Jacquot	e47f12f1d7	implement push PC to RSTK	2019-03-04 11:52:05 +01:00
Raphaël Jacquot	da3cce2c07	execute the first jump successfully, and start reading the next instruction	2019-03-03 22:38:56 +01:00
Raphaël Jacquot	631b7f9153	start implementing jump instructions	2019-03-03 20:48:56 +01:00
Raphaël Jacquot	6dd38500a8	add a counter to slow things down	2019-03-03 15:19:07 +01:00
Raphaël Jacquot	eeb5150159	add the beginnings of a PC and RSTK handler ... fix bad maths in the rom-gx-r module wire in the PC in the debugger and the control unit add an execute flag, to start execution of partially decoded instructions that need reading data from the instruction stream	2019-03-03 09:33:42 +01:00