Commit graph

8 commits

Author SHA1 Message Date
Raphael Jacquot
01429b4493 tested all the way to cycle 400 where transfers from memory need to be fixed in the bus controller 2019-02-17 21:20:18 +01:00
Raphael Jacquot
5c4bff0b5e rewrite the messy hadling of load_dp and dp_write 2019-02-17 20:23:43 +01:00
Raphael Jacquot
0d3c3ecd3e implement CONFIG
cleanup the bus controller
2019-02-17 19:29:39 +01:00
Raphael Jacquot
7a3a36bd25 implement the reset bus command 2019-02-17 15:03:36 +01:00
Raphael Jacquot
1c719a1828 cleanup and reorganization for readability 2019-02-17 12:57:38 +01:00
Raphael Jacquot
8fc7cde507 implement the pieces to replicate the bus data transfers for writing data out. 2019-02-17 12:05:38 +01:00
Raphael Jacquot
128921c364 start implementing the bus controller 2019-02-17 08:35:26 +01:00
Raphael Jacquot
500e013bf5 start on the bus controller 2019-02-16 22:38:44 +01:00