Raphael Jacquot
2bde756bfe
add the sysram module
2019-03-15 12:26:26 +01:00
Raphael Jacquot
a1b22269b2
add mmio
...
fix rtn instructions
decode block 14x
2019-03-14 22:20:03 +01:00
Raphael Jacquot
b2ae484450
implement the ALU as it should be
2019-03-14 21:47:05 +01:00
Raphaël Jacquot
f86a1d03c5
implement base alu functionnality
2019-03-06 12:16:34 +01:00
Raphaël Jacquot
7708d7a85c
attached serial port tentative
2019-03-04 14:40:31 +01:00
Raphaël Jacquot
eeb5150159
add the beginnings of a PC and RSTK handler
...
fix bad maths in the rom-gx-r module
wire in the PC in the debugger and the control unit
add an execute flag, to start execution of partially
decoded instructions that need reading data from the
instruction stream
2019-03-03 09:33:42 +01:00
Raphael Jacquot
c5355b4a90
enough was done to start feeding the decoder
2019-03-02 15:52:56 +01:00
Raphael Jacquot
8ce2d2a993
implement more of the bus controller
2019-03-02 13:22:09 +01:00
Raphael Jacquot
8866b8c175
starts complete rewrite
2019-02-24 23:30:57 +01:00
Raphael Jacquot
ebbea44c50
add clearing HST
2019-02-22 16:37:35 +01:00