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https://github.com/sxpert/hp-saturn
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add some commenting
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3cbd6ac5e1
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cd2b74dcc8
3 changed files with 38 additions and 20 deletions
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@ -68,7 +68,7 @@ saturn_control_unit control_unit (
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.o_program_data (ctrl_unit_prog_data),
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.o_no_read (ctrl_unit_no_read),
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.i_nibble (nibble_in),
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.i_nibble (i_bus_nibble_in),
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.o_error (ctrl_unit_error)
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);
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@ -108,7 +108,6 @@ assign o_debug_cycle = dbg_debug_cycle;
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reg [0:0] bus_error;
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reg [0:0] bus_busy;
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reg [3:0] nibble_in;
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/*
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* program list for the bus controller
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@ -118,11 +117,13 @@ reg [3:0] nibble_in;
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reg [4:0] bus_prog_addr;
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reg [4:0] bus_program[0:31];
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reg [4:0] next_bus_prog_addr;
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reg [0:0] more_to_write;
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always @(*) begin
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// $write("BUSCTRL0 %0d: [%d] write prog %d : %5b\n", i_phase, i_cycle_ctr, ctrl_unit_prog_addr, ctrl_unit_prog_data);
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bus_program[ctrl_unit_prog_addr] = ctrl_unit_prog_data;
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next_bus_prog_addr = bus_prog_addr + 5'd1;
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more_to_write = (bus_prog_addr != ctrl_unit_prog_addr);
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end
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/*
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@ -152,8 +153,8 @@ always @(posedge i_clk) begin
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/*
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* in this phase, we can send a command or data from the processor
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*/
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if (bus_prog_addr != ctrl_unit_prog_addr) begin
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$write("BUSCTRL %0d: [%d] %d : %5b ", i_phase, i_cycle_ctr, next_bus_prog_addr, bus_program[next_bus_prog_addr]);
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if (more_to_write) begin
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$write("BUSCTRL %0d: [%d] %0d : %5b ", i_phase, i_cycle_ctr, next_bus_prog_addr, bus_program[next_bus_prog_addr]);
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if (bus_program[next_bus_prog_addr][4]) $write("CMD : ");
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else $write("DATA : ");
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$write("%h\n", bus_program[next_bus_prog_addr][3:0]);
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@ -162,11 +163,13 @@ always @(posedge i_clk) begin
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o_bus_nibble_out <= bus_program[next_bus_prog_addr][3:0];
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o_bus_clk_en <= 1'b1;
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bus_busy <= 1'b1;
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end else begin
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if (!ctrl_unit_no_read) begin
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$display("BUSCTRL %0d: [%d] setting up read", i_phase, i_cycle_ctr);
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o_bus_clk_en <= 1'b1;
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end
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end
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/*
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* nothing to send, see if we can read, and do it
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*/
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if (!more_to_write && !ctrl_unit_no_read) begin
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// $display("BUSCTRL %0d: [%d] setting up read", i_phase, i_cycle_ctr);
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o_bus_clk_en <= 1'b1;
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end
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end
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4'b0010:
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@ -175,12 +178,8 @@ always @(posedge i_clk) begin
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* this phase is reserved for reading data from the bus
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*/
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if (o_bus_clk_en) begin
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$display("BUSCTRL %0d: [%d] lowering bus clock_en", i_phase, i_cycle_ctr);
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// $display("BUSCTRL %0d: [%d] lowering bus clock_en", i_phase, i_cycle_ctr);
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o_bus_clk_en <= 1'b0;
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if (!ctrl_unit_no_read) begin
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$display("BUSCTRL %0d: [%d] read %h", i_phase, i_cycle_ctr, i_bus_nibble_in);
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nibble_in <= i_bus_nibble_in;
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end
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end
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end
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4'b0100:
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@ -188,7 +187,7 @@ always @(posedge i_clk) begin
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/*
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* this phase is when the instruction decoder does it's job
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*/
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if ((bus_prog_addr == ctrl_unit_prog_addr) && bus_busy) begin
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if (!more_to_write && bus_busy) begin
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$display("BUSCTRL %0d: [%d] done sending the entire program", i_phase, i_cycle_ctr);
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bus_busy <= 1'b0;
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end
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@ -89,6 +89,13 @@ end
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always @(posedge i_clk) begin
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/************************
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*
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* we're just starting, load the PC into the controller and modules
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* this could also be used when loading the PC on jumps, need to identify conditions
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*
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*/
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if (!i_debug_cycle && just_reset && i_phases[3]) begin
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/* this happend right after reset */
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`ifdef SIM
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@ -109,6 +116,9 @@ always @(posedge i_clk) begin
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/* loop to fill the initial PC value in the program */
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if (!i_debug_cycle && !control_unit_ready && (bus_prog_addr != 5'b0)) begin
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/*
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* this should load the actual PC values...
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*/
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o_program_data <= 5'b0;
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o_program_address <= bus_prog_addr;
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bus_prog_addr <= bus_prog_addr + 1;
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@ -126,7 +136,12 @@ always @(posedge i_clk) begin
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`endif
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end
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/* this happend otherwise */
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/************************
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*
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* main execution loop
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*
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*/
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if (!i_debug_cycle && control_unit_ready && !i_bus_busy) begin
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// `ifdef SIM
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@ -140,6 +155,10 @@ always @(posedge i_clk) begin
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if (i_phases[2]) begin
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$display("CTRL %0d: [%d] interpreting %h", i_phase, i_cycle_ctr, i_nibble);
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end
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if (i_phases[3]) begin
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$display("CTRL %0d: [%d] start instruction execution", i_phase, i_cycle_ctr);
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end
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end
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if (i_reset) begin
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@ -34,16 +34,16 @@ reg [0:0] reset;
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wire [0:0] halt;
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initial begin
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$display("TOP : starting the simulation");
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$display("TOP : starting the simulation");
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clk = 0;
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reset = 1;
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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reset = 0;
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$display("TOP : reset done, waiting for instructions");
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$display("TOP : reset done, waiting for instructions");
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@(posedge halt);
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$display("TOP : instructed to stop, halt is %b", halt);
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$display("TOP : instructed to stop, halt is %b", halt);
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$finish;
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end
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