From cd2b74dcc8173cf04445a3ead3bfae95a4aa8e81 Mon Sep 17 00:00:00 2001 From: Raphael Jacquot Date: Sat, 2 Mar 2019 15:01:00 +0100 Subject: [PATCH] add some commenting --- saturn_bus_controller.v | 29 ++++++++++++++--------------- saturn_control_unit.v | 23 +++++++++++++++++++++-- saturn_top.v | 6 +++--- 3 files changed, 38 insertions(+), 20 deletions(-) diff --git a/saturn_bus_controller.v b/saturn_bus_controller.v index 9fe1454..d2c194c 100644 --- a/saturn_bus_controller.v +++ b/saturn_bus_controller.v @@ -68,7 +68,7 @@ saturn_control_unit control_unit ( .o_program_data (ctrl_unit_prog_data), .o_no_read (ctrl_unit_no_read), - .i_nibble (nibble_in), + .i_nibble (i_bus_nibble_in), .o_error (ctrl_unit_error) ); @@ -108,7 +108,6 @@ assign o_debug_cycle = dbg_debug_cycle; reg [0:0] bus_error; reg [0:0] bus_busy; -reg [3:0] nibble_in; /* * program list for the bus controller @@ -118,11 +117,13 @@ reg [3:0] nibble_in; reg [4:0] bus_prog_addr; reg [4:0] bus_program[0:31]; reg [4:0] next_bus_prog_addr; +reg [0:0] more_to_write; always @(*) begin // $write("BUSCTRL0 %0d: [%d] write prog %d : %5b\n", i_phase, i_cycle_ctr, ctrl_unit_prog_addr, ctrl_unit_prog_data); bus_program[ctrl_unit_prog_addr] = ctrl_unit_prog_data; next_bus_prog_addr = bus_prog_addr + 5'd1; + more_to_write = (bus_prog_addr != ctrl_unit_prog_addr); end /* @@ -152,8 +153,8 @@ always @(posedge i_clk) begin /* * in this phase, we can send a command or data from the processor */ - if (bus_prog_addr != ctrl_unit_prog_addr) begin - $write("BUSCTRL %0d: [%d] %d : %5b ", i_phase, i_cycle_ctr, next_bus_prog_addr, bus_program[next_bus_prog_addr]); + if (more_to_write) begin + $write("BUSCTRL %0d: [%d] %0d : %5b ", i_phase, i_cycle_ctr, next_bus_prog_addr, bus_program[next_bus_prog_addr]); if (bus_program[next_bus_prog_addr][4]) $write("CMD : "); else $write("DATA : "); $write("%h\n", bus_program[next_bus_prog_addr][3:0]); @@ -162,11 +163,13 @@ always @(posedge i_clk) begin o_bus_nibble_out <= bus_program[next_bus_prog_addr][3:0]; o_bus_clk_en <= 1'b1; bus_busy <= 1'b1; - end else begin - if (!ctrl_unit_no_read) begin - $display("BUSCTRL %0d: [%d] setting up read", i_phase, i_cycle_ctr); - o_bus_clk_en <= 1'b1; - end + end + /* + * nothing to send, see if we can read, and do it + */ + if (!more_to_write && !ctrl_unit_no_read) begin + // $display("BUSCTRL %0d: [%d] setting up read", i_phase, i_cycle_ctr); + o_bus_clk_en <= 1'b1; end end 4'b0010: @@ -175,12 +178,8 @@ always @(posedge i_clk) begin * this phase is reserved for reading data from the bus */ if (o_bus_clk_en) begin - $display("BUSCTRL %0d: [%d] lowering bus clock_en", i_phase, i_cycle_ctr); + // $display("BUSCTRL %0d: [%d] lowering bus clock_en", i_phase, i_cycle_ctr); o_bus_clk_en <= 1'b0; - if (!ctrl_unit_no_read) begin - $display("BUSCTRL %0d: [%d] read %h", i_phase, i_cycle_ctr, i_bus_nibble_in); - nibble_in <= i_bus_nibble_in; - end end end 4'b0100: @@ -188,7 +187,7 @@ always @(posedge i_clk) begin /* * this phase is when the instruction decoder does it's job */ - if ((bus_prog_addr == ctrl_unit_prog_addr) && bus_busy) begin + if (!more_to_write && bus_busy) begin $display("BUSCTRL %0d: [%d] done sending the entire program", i_phase, i_cycle_ctr); bus_busy <= 1'b0; end diff --git a/saturn_control_unit.v b/saturn_control_unit.v index 5168964..87d167f 100644 --- a/saturn_control_unit.v +++ b/saturn_control_unit.v @@ -89,6 +89,13 @@ end always @(posedge i_clk) begin + /************************ + * + * we're just starting, load the PC into the controller and modules + * this could also be used when loading the PC on jumps, need to identify conditions + * + */ + if (!i_debug_cycle && just_reset && i_phases[3]) begin /* this happend right after reset */ `ifdef SIM @@ -109,6 +116,9 @@ always @(posedge i_clk) begin /* loop to fill the initial PC value in the program */ if (!i_debug_cycle && !control_unit_ready && (bus_prog_addr != 5'b0)) begin + /* + * this should load the actual PC values... + */ o_program_data <= 5'b0; o_program_address <= bus_prog_addr; bus_prog_addr <= bus_prog_addr + 1; @@ -125,8 +135,13 @@ always @(posedge i_clk) begin $write("\n"); `endif end - - /* this happend otherwise */ + + /************************ + * + * main execution loop + * + */ + if (!i_debug_cycle && control_unit_ready && !i_bus_busy) begin // `ifdef SIM @@ -140,6 +155,10 @@ always @(posedge i_clk) begin if (i_phases[2]) begin $display("CTRL %0d: [%d] interpreting %h", i_phase, i_cycle_ctr, i_nibble); end + + if (i_phases[3]) begin + $display("CTRL %0d: [%d] start instruction execution", i_phase, i_cycle_ctr); + end end if (i_reset) begin diff --git a/saturn_top.v b/saturn_top.v index 849e747..d41d67a 100644 --- a/saturn_top.v +++ b/saturn_top.v @@ -34,16 +34,16 @@ reg [0:0] reset; wire [0:0] halt; initial begin - $display("TOP : starting the simulation"); + $display("TOP : starting the simulation"); clk = 0; reset = 1; @(posedge clk); @(posedge clk); @(posedge clk); reset = 0; - $display("TOP : reset done, waiting for instructions"); + $display("TOP : reset done, waiting for instructions"); @(posedge halt); - $display("TOP : instructed to stop, halt is %b", halt); + $display("TOP : instructed to stop, halt is %b", halt); $finish; end