add the serial port to the complie

change speed to 115200
This commit is contained in:
Raphael Jacquot 2019-03-04 14:53:48 +01:00
parent 7708d7a85c
commit 5716904ac8
2 changed files with 9 additions and 2 deletions

View file

@ -1,4 +1,5 @@
read_verilog -I. saturn_top.v read_verilog -I. saturn_top.v
read_verilog -I. saturn_serial.v
read_verilog -I. saturn_bus.v read_verilog -I. saturn_bus.v
read_verilog -I. saturn_hp48gx_rom.v read_verilog -I. saturn_hp48gx_rom.v
read_verilog -I. saturn_bus_controller.v read_verilog -I. saturn_bus_controller.v

View file

@ -51,8 +51,14 @@ reg [9:0] data_reg;
`define BIT_DELAY_START 13'h0 `define BIT_DELAY_START 13'h0
`define BIT_DELAY_TEST 0 `define BIT_DELAY_TEST 0
`else `else
`define BIT_DELAY_START 13'h54D /* 9600 */
`define BIT_DELAY_TEST 12 // `define BIT_DELAY_START 13'h54D
//`define BIT_DELAY_TEST 12
/* 115200 */
`define BIT_DELAY_START 13'h27
`define BIT_DELAY_TEST 8
`endif `endif
reg [12:0] bit_delay; reg [12:0] bit_delay;