mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-27 09:58:16 +01:00
92 lines
No EOL
2.1 KiB
Verilog
92 lines
No EOL
2.1 KiB
Verilog
/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`default_nettype none
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module saturn_serial (
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i_clk,
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i_char_to_send,
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i_char_valid,
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o_serial_tx,
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o_serial_busy
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);
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input wire [0:0] i_clk;
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input wire [7:0] i_char_to_send;
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input wire [0:0] i_char_valid;
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output wire [0:0] o_serial_tx;
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output wire [0:0] o_serial_busy;
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/*
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*
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*/
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reg [9:0] clocking_reg;
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reg [9:0] data_reg;
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`ifdef SIM
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`define BIT_DELAY_START 13'h0
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`define BIT_DELAY_TEST 0
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`else
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/* 9600 */
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// `define BIT_DELAY_START 13'h54D
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//`define BIT_DELAY_TEST 12
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/* 115200 */
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`define BIT_DELAY_START 13'h27
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`define BIT_DELAY_TEST 8
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`endif
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reg [12:0] bit_delay;
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initial begin
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bit_delay <= `BIT_DELAY_START;
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clocking_reg <= {10{1'b1}};
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data_reg <= {10{1'b1}};
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end
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assign o_serial_busy = !clocking_reg[9];
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assign o_serial_tx = data_reg[9];
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always @(posedge i_clk) begin
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// $display("%0d", bit_delay);
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if (i_char_valid && !o_serial_busy) begin
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$display("serial storing char %c", i_char_to_send);
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clocking_reg <= 10'b0;
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data_reg <= { 1'b0, i_char_to_send, 1'b1 };
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bit_delay <= `BIT_DELAY_START;
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end
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if (!i_char_valid && o_serial_busy && bit_delay[`BIT_DELAY_TEST]) begin
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$display("%b %b", o_serial_tx, data_reg);
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clocking_reg <= { clocking_reg[8:0], 1'b1};
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data_reg <= { data_reg[8:0], 1'b1};
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bit_delay <= `BIT_DELAY_START;
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end
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bit_delay <= bit_delay + 13'd1;
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end
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endmodule |