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https://github.com/sxpert/hp-saturn
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ok, we're getting somewhere
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4 changed files with 44 additions and 13 deletions
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@ -27,6 +27,8 @@ module saturn_bus (
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o_halt,
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o_phase,
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o_cycle_ctr,
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o_instr_decoded,
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o_debug_cycle,
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o_char_to_send,
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o_char_counter,
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o_char_valid,
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@ -40,6 +42,11 @@ input wire [0:0] i_reset;
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output wire [0:0] o_halt;
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output wire [1:0] o_phase;
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output wire [31:0] o_cycle_ctr;
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output wire [0:0] o_instr_decoded;
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output wire [0:0] o_debug_cycle;
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assign o_debug_cycle = dbg_debug_cycle;
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output wire [7:0] o_char_to_send;
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output wire [9:0] o_char_counter;
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output wire [0:0] o_char_valid;
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@ -94,6 +101,7 @@ saturn_bus_controller bus_controller (
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// more ports should show up to allow for output to the serial port of debug information
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.o_debug_cycle (dbg_debug_cycle),
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.o_instr_decoded (o_instr_decoded),
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.o_char_to_send (o_char_to_send),
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.o_char_counter (o_char_counter),
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.o_char_valid (o_char_valid),
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@ -34,6 +34,7 @@ module saturn_bus_controller (
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i_bus_nibble_in,
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o_debug_cycle,
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o_instr_decoded,
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o_char_to_send,
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o_char_counter,
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o_char_valid,
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@ -55,6 +56,8 @@ output reg [3:0] o_bus_nibble_out;
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input wire [3:0] i_bus_nibble_in;
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output wire [0:0] o_debug_cycle;
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output wire [0:0] o_instr_decoded;
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assign o_instr_decoded = dec_instr_decoded;
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output wire [7:0] o_char_to_send;
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output wire [9:0] o_char_counter;
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output wire [0:0] o_char_valid;
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@ -516,7 +516,7 @@ always @(posedge i_clk) begin
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end
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/* writes the chars to the serial port */
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if (i_clk_en && write_out && !o_char_valid && !i_serial_busy) begin
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if (write_out && !o_char_valid && !i_serial_busy) begin
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o_char_send <= ~o_char_send;
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o_char_to_send <= registers_str[counter];
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o_char_valid <= 1'b1;
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@ -534,6 +534,18 @@ always @(posedge i_clk) begin
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end
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end
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if (i_bus_read_valid) begin
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o_char_send <= ~o_char_send;
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o_char_to_send <= hex[i_bus_nibble_in];
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o_char_valid <= 1'b1;
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end
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if (i_clk_en && i_instr_decoded) begin
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o_char_send <= ~o_char_send;
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o_char_to_send <= "|";
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o_char_valid <= 1'b1;
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end
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/* clear the char clock enable */
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if (o_char_valid) begin
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o_char_valid <= 1'b0;
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10
saturn_top.v
10
saturn_top.v
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@ -122,6 +122,8 @@ saturn_bus main_bus (
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.o_halt (halt),
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.o_phase (phase),
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.o_cycle_ctr (cycle_ctr),
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.o_instr_decoded (instr_decoded),
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.o_debug_cycle (debug_cycle),
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.o_char_to_send (char_to_send),
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.o_char_counter (char_counter),
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.o_char_valid (char_valid),
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@ -144,6 +146,8 @@ reg [0:0] reset;
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wire [0:0] halt;
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wire [1:0] phase;
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wire [31:0] cycle_ctr;
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wire [0:0] instr_decoded;
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wire [0:0] debug_cycle;
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wire [7:0] char_to_send;
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wire [9:0] char_counter;
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wire [0:0] char_valid;
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@ -168,7 +172,7 @@ wire [0:0] serial_busy;
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// `define TEST_BIT 20
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initial begin
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led = 8'h01;
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led = 8'h00;
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delay = `DELAY_START;
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reset = 1'b1;
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clk2 = 1'b0;
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@ -182,7 +186,11 @@ always @(posedge clk_25mhz) begin
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led[7] <= halt;
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led[6] <= char_send;
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led[5] <= serial_busy;
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led[4] <= debug_cycle;
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led[3] <= clk_en;
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led[2] <= instr_decoded;
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led[1:0] <= phase;
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end
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endmodule
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