From 4d578f8f181e32b38f5794caf84b876107bc6c03 Mon Sep 17 00:00:00 2001 From: Raphael Jacquot Date: Mon, 4 Mar 2019 21:10:12 +0100 Subject: [PATCH] ok, we're getting somewhere --- saturn_bus.v | 8 ++++++++ saturn_bus_controller.v | 3 +++ saturn_debugger.v | 14 +++++++++++++- saturn_top.v | 32 ++++++++++++++++++++------------ 4 files changed, 44 insertions(+), 13 deletions(-) diff --git a/saturn_bus.v b/saturn_bus.v index de6f693..7f3d706 100644 --- a/saturn_bus.v +++ b/saturn_bus.v @@ -27,6 +27,8 @@ module saturn_bus ( o_halt, o_phase, o_cycle_ctr, + o_instr_decoded, + o_debug_cycle, o_char_to_send, o_char_counter, o_char_valid, @@ -40,6 +42,11 @@ input wire [0:0] i_reset; output wire [0:0] o_halt; output wire [1:0] o_phase; output wire [31:0] o_cycle_ctr; + +output wire [0:0] o_instr_decoded; +output wire [0:0] o_debug_cycle; +assign o_debug_cycle = dbg_debug_cycle; + output wire [7:0] o_char_to_send; output wire [9:0] o_char_counter; output wire [0:0] o_char_valid; @@ -94,6 +101,7 @@ saturn_bus_controller bus_controller ( // more ports should show up to allow for output to the serial port of debug information .o_debug_cycle (dbg_debug_cycle), + .o_instr_decoded (o_instr_decoded), .o_char_to_send (o_char_to_send), .o_char_counter (o_char_counter), .o_char_valid (o_char_valid), diff --git a/saturn_bus_controller.v b/saturn_bus_controller.v index d5e2b55..846429d 100644 --- a/saturn_bus_controller.v +++ b/saturn_bus_controller.v @@ -34,6 +34,7 @@ module saturn_bus_controller ( i_bus_nibble_in, o_debug_cycle, + o_instr_decoded, o_char_to_send, o_char_counter, o_char_valid, @@ -55,6 +56,8 @@ output reg [3:0] o_bus_nibble_out; input wire [3:0] i_bus_nibble_in; output wire [0:0] o_debug_cycle; +output wire [0:0] o_instr_decoded; +assign o_instr_decoded = dec_instr_decoded; output wire [7:0] o_char_to_send; output wire [9:0] o_char_counter; output wire [0:0] o_char_valid; diff --git a/saturn_debugger.v b/saturn_debugger.v index 2e7d8c2..0b4e79c 100644 --- a/saturn_debugger.v +++ b/saturn_debugger.v @@ -516,7 +516,7 @@ always @(posedge i_clk) begin end /* writes the chars to the serial port */ - if (i_clk_en && write_out && !o_char_valid && !i_serial_busy) begin + if (write_out && !o_char_valid && !i_serial_busy) begin o_char_send <= ~o_char_send; o_char_to_send <= registers_str[counter]; o_char_valid <= 1'b1; @@ -534,6 +534,18 @@ always @(posedge i_clk) begin end end + if (i_bus_read_valid) begin + o_char_send <= ~o_char_send; + o_char_to_send <= hex[i_bus_nibble_in]; + o_char_valid <= 1'b1; + end + + if (i_clk_en && i_instr_decoded) begin + o_char_send <= ~o_char_send; + o_char_to_send <= "|"; + o_char_valid <= 1'b1; + end + /* clear the char clock enable */ if (o_char_valid) begin o_char_valid <= 1'b0; diff --git a/saturn_top.v b/saturn_top.v index fe8096f..77c288b 100644 --- a/saturn_top.v +++ b/saturn_top.v @@ -116,17 +116,19 @@ output wire [0:0] ftdi_rxd; assign wifi_gpio0 = btn[0]; saturn_bus main_bus ( - .i_clk (clk_25mhz), - .i_clk_en (clk_en), - .i_reset (reset), - .o_halt (halt), - .o_phase (phase), - .o_cycle_ctr (cycle_ctr), - .o_char_to_send (char_to_send), - .o_char_counter (char_counter), - .o_char_valid (char_valid), - .o_char_send (char_send), - .i_serial_busy (serial_busy) + .i_clk (clk_25mhz), + .i_clk_en (clk_en), + .i_reset (reset), + .o_halt (halt), + .o_phase (phase), + .o_cycle_ctr (cycle_ctr), + .o_instr_decoded (instr_decoded), + .o_debug_cycle (debug_cycle), + .o_char_to_send (char_to_send), + .o_char_counter (char_counter), + .o_char_valid (char_valid), + .o_char_send (char_send), + .i_serial_busy (serial_busy) ); saturn_serial serial_port ( @@ -144,6 +146,8 @@ reg [0:0] reset; wire [0:0] halt; wire [1:0] phase; wire [31:0] cycle_ctr; +wire [0:0] instr_decoded; +wire [0:0] debug_cycle; wire [7:0] char_to_send; wire [9:0] char_counter; wire [0:0] char_valid; @@ -168,7 +172,7 @@ wire [0:0] serial_busy; // `define TEST_BIT 20 initial begin - led = 8'h01; + led = 8'h00; delay = `DELAY_START; reset = 1'b1; clk2 = 1'b0; @@ -182,7 +186,11 @@ always @(posedge clk_25mhz) begin led[7] <= halt; led[6] <= char_send; led[5] <= serial_busy; + led[4] <= debug_cycle; led[3] <= clk_en; + led[2] <= instr_decoded; + + led[1:0] <= phase; end endmodule