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ok, we're getting somewhere

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This commit is contained in:
Raphael Jacquot 2019-03-04 21:10:12 +01:00
parent 7e0f4a9c0f
commit 4d578f8f18
4 changed files with 44 additions and 13 deletions
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8
saturn_bus.v
View file

@ -27,6 +27,8 @@ module saturn_bus (
o_halt, o_halt,
o_phase, o_phase,
o_cycle_ctr, o_cycle_ctr,
o_instr_decoded,
o_debug_cycle,
o_char_to_send, o_char_to_send,
o_char_counter, o_char_counter,
o_char_valid, o_char_valid,
@ -40,6 +42,11 @@ input wire [0:0] i_reset;
output wire [0:0] o_halt; output wire [0:0] o_halt;
output wire [1:0] o_phase; output wire [1:0] o_phase;
output wire [31:0] o_cycle_ctr; output wire [31:0] o_cycle_ctr;
output wire [0:0] o_instr_decoded;
output wire [0:0] o_debug_cycle;
assign o_debug_cycle = dbg_debug_cycle;
output wire [7:0] o_char_to_send; output wire [7:0] o_char_to_send;
output wire [9:0] o_char_counter; output wire [9:0] o_char_counter;
output wire [0:0] o_char_valid; output wire [0:0] o_char_valid;
@ -94,6 +101,7 @@ saturn_bus_controller bus_controller (
// more ports should show up to allow for output to the serial port of debug information // more ports should show up to allow for output to the serial port of debug information
.o_debug_cycle (dbg_debug_cycle), .o_debug_cycle (dbg_debug_cycle),
.o_instr_decoded (o_instr_decoded),
.o_char_to_send (o_char_to_send), .o_char_to_send (o_char_to_send),
.o_char_counter (o_char_counter), .o_char_counter (o_char_counter),
.o_char_valid (o_char_valid), .o_char_valid (o_char_valid),

3
saturn_bus_controller.v
View file

@ -34,6 +34,7 @@ module saturn_bus_controller (
i_bus_nibble_in, i_bus_nibble_in,
o_debug_cycle, o_debug_cycle,
o_instr_decoded,
o_char_to_send, o_char_to_send,
o_char_counter, o_char_counter,
o_char_valid, o_char_valid,
@ -55,6 +56,8 @@ output reg [3:0] o_bus_nibble_out;
input wire [3:0] i_bus_nibble_in; input wire [3:0] i_bus_nibble_in;
output wire [0:0] o_debug_cycle; output wire [0:0] o_debug_cycle;
output wire [0:0] o_instr_decoded;
assign o_instr_decoded = dec_instr_decoded;
output wire [7:0] o_char_to_send; output wire [7:0] o_char_to_send;
output wire [9:0] o_char_counter; output wire [9:0] o_char_counter;
output wire [0:0] o_char_valid; output wire [0:0] o_char_valid;

14
saturn_debugger.v
View file

@ -516,7 +516,7 @@ always @(posedge i_clk) begin
end end
/* writes the chars to the serial port */ /* writes the chars to the serial port */
if (i_clk_en && write_out && !o_char_valid && !i_serial_busy) begin if (write_out && !o_char_valid && !i_serial_busy) begin
o_char_send <= ~o_char_send; o_char_send <= ~o_char_send;
o_char_to_send <= registers_str[counter]; o_char_to_send <= registers_str[counter];
o_char_valid <= 1'b1; o_char_valid <= 1'b1;
@ -534,6 +534,18 @@ always @(posedge i_clk) begin
end end
end end
if (i_bus_read_valid) begin
o_char_send <= ~o_char_send;
o_char_to_send <= hex[i_bus_nibble_in];
o_char_valid <= 1'b1;
end
if (i_clk_en && i_instr_decoded) begin
o_char_send <= ~o_char_send;
o_char_to_send <= "|";
o_char_valid <= 1'b1;
end
/* clear the char clock enable */ /* clear the char clock enable */
if (o_char_valid) begin if (o_char_valid) begin
o_char_valid <= 1'b0; o_char_valid <= 1'b0;

32
saturn_top.v
View file

@ -116,17 +116,19 @@ output wire [0:0] ftdi_rxd;
assign wifi_gpio0 = btn[0]; assign wifi_gpio0 = btn[0];
saturn_bus main_bus ( saturn_bus main_bus (
.i_clk (clk_25mhz), .i_clk (clk_25mhz),
.i_clk_en (clk_en), .i_clk_en (clk_en),
.i_reset (reset), .i_reset (reset),
.o_halt (halt), .o_halt (halt),
.o_phase (phase), .o_phase (phase),
.o_cycle_ctr (cycle_ctr), .o_cycle_ctr (cycle_ctr),
.o_char_to_send (char_to_send), .o_instr_decoded (instr_decoded),
.o_char_counter (char_counter), .o_debug_cycle (debug_cycle),
.o_char_valid (char_valid), .o_char_to_send (char_to_send),
.o_char_send (char_send), .o_char_counter (char_counter),
.i_serial_busy (serial_busy) .o_char_valid (char_valid),
.o_char_send (char_send),
.i_serial_busy (serial_busy)
); );
saturn_serial serial_port ( saturn_serial serial_port (
@ -144,6 +146,8 @@ reg [0:0] reset;
wire [0:0] halt; wire [0:0] halt;
wire [1:0] phase; wire [1:0] phase;
wire [31:0] cycle_ctr; wire [31:0] cycle_ctr;
wire [0:0] instr_decoded;
wire [0:0] debug_cycle;
wire [7:0] char_to_send; wire [7:0] char_to_send;
wire [9:0] char_counter; wire [9:0] char_counter;
wire [0:0] char_valid; wire [0:0] char_valid;
@ -168,7 +172,7 @@ wire [0:0] serial_busy;
// `define TEST_BIT 20 // `define TEST_BIT 20
initial begin initial begin
led = 8'h01; led = 8'h00;
delay = `DELAY_START; delay = `DELAY_START;
reset = 1'b1; reset = 1'b1;
clk2 = 1'b0; clk2 = 1'b0;
@ -182,7 +186,11 @@ always @(posedge clk_25mhz) begin
led[7] <= halt; led[7] <= halt;
led[6] <= char_send; led[6] <= char_send;
led[5] <= serial_busy; led[5] <= serial_busy;
led[4] <= debug_cycle;
led[3] <= clk_en; led[3] <= clk_en;
led[2] <= instr_decoded;
led[1:0] <= phase;
end end
endmodule endmodule