mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-24 21:59:33 +01:00
cleanups
This commit is contained in:
Raphael Jacquot
parent
2bde756bfe
commit
194415a6ed
4 changed files with 25 additions and 39 deletions
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@ -274,7 +274,6 @@ saturn_regs_pc_rstk regs_pc_rstk (
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.i_cycle_ctr (i_cycle_ctr),
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.i_bus_busy (i_bus_busy),
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// .i_alu_busy (o_alu_busy),
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.i_exec_unit_busy (o_exec_unit_busy),
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.i_nibble (i_nibble),
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@ -282,10 +281,8 @@ saturn_regs_pc_rstk regs_pc_rstk (
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.i_jump_length (dec_jump_length),
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.i_block_0x (dec_block_0x),
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.i_push_pc (dec_push_pc),
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.i_rtn_instr (inst_rtn),
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.o_current_pc (reg_PC),
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.o_reload_pc (reload_PC),
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.i_dbg_rstk_ptr (i_dbg_rstk_ptr),
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.o_dbg_rstk_val (o_dbg_rstk_val),
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@ -363,7 +360,6 @@ wire [0:0] alu_done = alu_calc_done || alu_save_done;
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/*
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* should we reload the PC after it has been changed
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*/
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wire [0:0] reload_PC;
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always @(i_dbg_register, i_dbg_reg_ptr) begin
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case (i_dbg_register)
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@ -395,7 +391,6 @@ reg [0:0] control_unit_ready;
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reg [5:0] bus_program[0:31];
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reg [4:0] bus_prog_addr;
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reg [2:0] addr_nibble_ptr;
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reg [0:0] load_pc_loop;
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reg [0:0] send_reg_PC;
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reg [0:0] send_reg_C_A;
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@ -409,7 +404,7 @@ reg [3:0] mem_access_ptr;
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reg [0:0] send_pc_read;
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wire [3:0] reg_PC_nibble = reg_PC[addr_nibble_ptr*4+:4];
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//wire [3:0] reg_PC_nibble = reg_PC[addr_nibble_ptr*4+:4];
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assign o_program_data = bus_program[i_program_address];
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assign o_program_address = bus_prog_addr;
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@ -423,7 +418,6 @@ initial begin
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control_unit_ready = 1'b0;
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bus_prog_addr = 5'd0;
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addr_nibble_ptr = 3'd0;
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load_pc_loop = 1'b0;
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send_reg_PC = 1'b0;
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send_reg_C_A = 1'b0;
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@ -454,8 +448,8 @@ always @(posedge i_clk) begin
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reg_B[init_counter] <= 4'h0;
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reg_C[init_counter] <= 4'h0;
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reg_D[init_counter] <= 4'h0;
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reg_D0[init_counter] <= 4'h0;
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reg_D1[init_counter] <= 4'h0;
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reg_D0[init_counter[2:0]] <= 4'h0;
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reg_D1[init_counter[2:0]] <= 4'h0;
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reg_R0[init_counter] <= 4'h0;
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reg_R1[init_counter] <= 4'h0;
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reg_R2[init_counter] <= 4'h0;
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@ -947,7 +941,6 @@ always @(posedge i_clk) begin
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control_unit_ready <= 1'b0;
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bus_prog_addr <= 5'd0;
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addr_nibble_ptr <= 3'd0;
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load_pc_loop <= 1'b0;
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send_reg_PC <= 1'b0;
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send_reg_C_A <= 1'b0;
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@ -159,8 +159,6 @@ always @(posedge i_clk) begin
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o_bus_nibble_out <= sysram_data[address];
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end
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reg [0:0] junk_bit_0;
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always @(posedge i_clk) begin
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if (can_write) begin
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sysram_data[address] <= i_bus_nibble_in;
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@ -368,8 +366,7 @@ always @(posedge i_clk) begin
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end
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// Verilator lint_off UNUSED
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wire [(20 -`SYSRAM_BITS):0] unused;
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assign unused = { junk_bit_0, access_pointer[19:`SYSRAM_BITS] };
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wire [(19 -`SYSRAM_BITS):0] unused = { access_pointer[19:`SYSRAM_BITS] };
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// Verilator lint_on UNUSED
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endmodule
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@ -29,7 +29,6 @@ module saturn_regs_pc_rstk (
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i_cycle_ctr,
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i_bus_busy,
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i_alu_busy,
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i_exec_unit_busy,
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i_nibble,
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@ -37,7 +36,6 @@ module saturn_regs_pc_rstk (
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i_jump_length,
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i_block_0x,
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i_push_pc,
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i_rtn_instr,
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o_current_pc,
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o_reload_pc,
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@ -52,11 +50,15 @@ input wire [0:0] i_clk;
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input wire [0:0] i_clk_en;
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input wire [0:0] i_reset;
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input wire [3:0] i_phases;
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// Verilator lint_off UNUSED
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wire [0:0] unused = { i_phases[0] };
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// Verilator lint_on UNUSED
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input wire [1:0] i_phase;
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input wire [31:0] i_cycle_ctr;
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input wire [0:0] i_bus_busy;
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input wire [0:0] i_alu_busy;
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input wire [0:0] i_exec_unit_busy;
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input wire [3:0] i_nibble;
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@ -64,7 +66,6 @@ input wire [0:0] i_jump_instr;
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input wire [2:0] i_jump_length;
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input wire [0:0] i_block_0x;
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input wire [0:0] i_push_pc;
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input wire [0:0] i_rtn_instr;
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output wire [19:0] o_current_pc;
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output reg [0:0] o_reload_pc;
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@ -91,16 +92,14 @@ wire [0:0] do_jump_instr = !just_reset && i_jump_instr;
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reg [0:0] just_reset;
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reg [2:0] init_counter;
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reg [0:0] jump_decode;
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reg [0:0] jump_exec;
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reg [2:0] jump_counter;
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reg [19:0] jump_base;
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reg [19:0] jump_offset;
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reg [19:0] jump_rel_addr;
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reg [15:0] jump_offset;
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wire [0:0] jump_rel2 = i_jump_instr && (i_jump_length == 3'd1);
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wire [0:0] jump_rel3 = i_jump_instr && (i_jump_length == 3'd2);
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wire [0:0] jump_rel4 = i_jump_instr && (i_jump_length == 3'd3);
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wire [0:0] jump_abs5 = i_jump_instr && (i_jump_length == 3'd4);
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//wire [0:0] jump_abs5 = i_jump_instr && (i_jump_length == 3'd4);
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wire [0:0] jump_relative = jump_rel2 || jump_rel3 || jump_rel4;
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/* this appears to be SLOW */
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@ -135,7 +134,6 @@ initial begin
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just_reset = 1'b1;
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init_counter = 3'd0;
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jump_decode = 1'b0;
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jump_exec = 1'b0;
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jump_counter = 3'd0;
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reg_PC = 20'h00000;
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reg_rstk_ptr = 3'd7;
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@ -143,7 +141,6 @@ initial begin
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addr_to_return_to = 20'b0;
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rstk_ptr_after_pop = 3'd0;
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rstk_ptr_to_push_at = 3'd0;
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jump_rel_addr = 20'b0;
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end
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/*
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@ -210,7 +207,7 @@ always @(posedge i_clk) begin
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/* one step of the calculation (one nibble of data came in) */
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if (i_phases[2] && do_jump_instr && jump_decode) begin
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$display("PC_RSTK %0d: [%d] decode jump %0d/%0d %h %5h", i_phase, i_cycle_ctr, i_jump_length, jump_counter, i_nibble, jump_next_offset);
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jump_offset <= jump_next_offset;
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jump_offset <= jump_next_offset[15:0];
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jump_counter <= jump_counter + 3'd1;
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if (jump_counter == i_jump_length) begin
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$write("PC_RSTK %0d: [%d] execute jump(%0d) jump_base %h jump_next_offset %h", i_phase, i_cycle_ctr, i_jump_length, jump_base, jump_next_offset);
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@ -258,26 +255,15 @@ always @(posedge i_clk) begin
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end
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// if (i_phases[0] && i_clk_en) begin
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// $write("RSTK : ptr %0d | ", reg_rstk_ptr);
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// for (tmp_ctr = 4'd0; tmp_ctr < 4'd8; tmp_ctr = tmp_ctr + 4'd1)
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// $write("%0d => %5h | ", tmp_ctr, reg_RSTK[tmp_ctr]);
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// $write("\n");
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// end
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if (i_reset) begin
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o_reload_pc <= 1'b0;
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just_reset <= 1'b1;
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init_counter <= 3'd0;
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jump_decode <= 1'b0;
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jump_exec <= 1'b0;
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jump_counter <= 3'd0;
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reg_PC <= 20'h00000;
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reg_rstk_ptr <= 3'd7;
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end
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end
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reg [3:0] tmp_ctr;
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endmodule
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14
saturn_top.v
14
saturn_top.v
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@ -112,6 +112,10 @@ output reg [7:0] led;
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output wire [0:0] wifi_gpio0;
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output wire [0:0] ftdi_rxd;
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// Verilator lint_off UNUSED
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wire [4:0] unused = { btn[6:2] };
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// Verilator lint_on UNUSED
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/* this is necessary, otherwise, the esp32 module reboots the fpga in passthrough */
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assign wifi_gpio0 = btn[0];
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@ -140,16 +144,23 @@ saturn_serial serial_port (
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);
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reg [25:0] delay;
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reg [0:0] clk2;
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reg [0:0] clk_en;
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reg [0:0] reset;
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wire [0:0] halt;
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wire [1:0] phase;
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// Verilator lint_off UNUSED
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wire [31:0] cycle_ctr;
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// Verilator lint_on UNUSED
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wire [0:0] instr_decoded;
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wire [0:0] debug_cycle;
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wire [7:0] char_to_send;
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// Verilator lint_off UNUSED
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wire [9:0] char_counter;
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// Verilator lint_on UNUSED
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wire [0:0] char_valid;
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wire [0:0] char_send;
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wire [0:0] serial_busy;
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@ -175,7 +186,6 @@ initial begin
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led = 8'h00;
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delay = `DELAY_START;
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reset = 1'b1;
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clk2 = 1'b0;
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end
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always @(posedge clk_25mhz) begin
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