From 194415a6ed37a6567a44e8ce84a1687597536a0d Mon Sep 17 00:00:00 2001 From: Raphael Jacquot Date: Fri, 15 Mar 2019 13:31:37 +0100 Subject: [PATCH] cleanups --- saturn_control_unit.v | 15 ++++----------- saturn_hp48gx_sysram.v | 5 +---- saturn_regs_pc_rstk.v | 30 ++++++++---------------------- saturn_top.v | 14 ++++++++++++-- 4 files changed, 25 insertions(+), 39 deletions(-) diff --git a/saturn_control_unit.v b/saturn_control_unit.v index c3df737..769d4ed 100644 --- a/saturn_control_unit.v +++ b/saturn_control_unit.v @@ -274,7 +274,6 @@ saturn_regs_pc_rstk regs_pc_rstk ( .i_cycle_ctr (i_cycle_ctr), .i_bus_busy (i_bus_busy), - // .i_alu_busy (o_alu_busy), .i_exec_unit_busy (o_exec_unit_busy), .i_nibble (i_nibble), @@ -282,10 +281,8 @@ saturn_regs_pc_rstk regs_pc_rstk ( .i_jump_length (dec_jump_length), .i_block_0x (dec_block_0x), .i_push_pc (dec_push_pc), - .i_rtn_instr (inst_rtn), .o_current_pc (reg_PC), - .o_reload_pc (reload_PC), .i_dbg_rstk_ptr (i_dbg_rstk_ptr), .o_dbg_rstk_val (o_dbg_rstk_val), @@ -348,7 +345,7 @@ reg [0:0] alu_calc_run; reg [3:0] alu_calc_pos; reg [3:0] alu_calc_res_1_val; reg [3:0] alu_calc_res_2_val; -reg [0:0] alu_calc_carry; +reg [0:0] alu_calc_carry; reg [0:0] alu_calc_done; reg [0:0] alu_save_run; @@ -363,7 +360,6 @@ wire [0:0] alu_done = alu_calc_done || alu_save_done; /* * should we reload the PC after it has been changed */ -wire [0:0] reload_PC; always @(i_dbg_register, i_dbg_reg_ptr) begin case (i_dbg_register) @@ -395,7 +391,6 @@ reg [0:0] control_unit_ready; reg [5:0] bus_program[0:31]; reg [4:0] bus_prog_addr; reg [2:0] addr_nibble_ptr; -reg [0:0] load_pc_loop; reg [0:0] send_reg_PC; reg [0:0] send_reg_C_A; @@ -409,7 +404,7 @@ reg [3:0] mem_access_ptr; reg [0:0] send_pc_read; -wire [3:0] reg_PC_nibble = reg_PC[addr_nibble_ptr*4+:4]; +//wire [3:0] reg_PC_nibble = reg_PC[addr_nibble_ptr*4+:4]; assign o_program_data = bus_program[i_program_address]; assign o_program_address = bus_prog_addr; @@ -423,7 +418,6 @@ initial begin control_unit_ready = 1'b0; bus_prog_addr = 5'd0; addr_nibble_ptr = 3'd0; - load_pc_loop = 1'b0; send_reg_PC = 1'b0; send_reg_C_A = 1'b0; @@ -454,8 +448,8 @@ always @(posedge i_clk) begin reg_B[init_counter] <= 4'h0; reg_C[init_counter] <= 4'h0; reg_D[init_counter] <= 4'h0; - reg_D0[init_counter] <= 4'h0; - reg_D1[init_counter] <= 4'h0; + reg_D0[init_counter[2:0]] <= 4'h0; + reg_D1[init_counter[2:0]] <= 4'h0; reg_R0[init_counter] <= 4'h0; reg_R1[init_counter] <= 4'h0; reg_R2[init_counter] <= 4'h0; @@ -947,7 +941,6 @@ always @(posedge i_clk) begin control_unit_ready <= 1'b0; bus_prog_addr <= 5'd0; addr_nibble_ptr <= 3'd0; - load_pc_loop <= 1'b0; send_reg_PC <= 1'b0; send_reg_C_A <= 1'b0; diff --git a/saturn_hp48gx_sysram.v b/saturn_hp48gx_sysram.v index c34bb14..35e636a 100644 --- a/saturn_hp48gx_sysram.v +++ b/saturn_hp48gx_sysram.v @@ -159,8 +159,6 @@ always @(posedge i_clk) begin o_bus_nibble_out <= sysram_data[address]; end -reg [0:0] junk_bit_0; - always @(posedge i_clk) begin if (can_write) begin sysram_data[address] <= i_bus_nibble_in; @@ -368,8 +366,7 @@ always @(posedge i_clk) begin end // Verilator lint_off UNUSED -wire [(20 -`SYSRAM_BITS):0] unused; -assign unused = { junk_bit_0, access_pointer[19:`SYSRAM_BITS] }; +wire [(19 -`SYSRAM_BITS):0] unused = { access_pointer[19:`SYSRAM_BITS] }; // Verilator lint_on UNUSED endmodule \ No newline at end of file diff --git a/saturn_regs_pc_rstk.v b/saturn_regs_pc_rstk.v index 8a6919b..f0b46e9 100644 --- a/saturn_regs_pc_rstk.v +++ b/saturn_regs_pc_rstk.v @@ -29,7 +29,6 @@ module saturn_regs_pc_rstk ( i_cycle_ctr, i_bus_busy, - i_alu_busy, i_exec_unit_busy, i_nibble, @@ -37,7 +36,6 @@ module saturn_regs_pc_rstk ( i_jump_length, i_block_0x, i_push_pc, - i_rtn_instr, o_current_pc, o_reload_pc, @@ -52,11 +50,15 @@ input wire [0:0] i_clk; input wire [0:0] i_clk_en; input wire [0:0] i_reset; input wire [3:0] i_phases; + +// Verilator lint_off UNUSED +wire [0:0] unused = { i_phases[0] }; +// Verilator lint_on UNUSED + input wire [1:0] i_phase; input wire [31:0] i_cycle_ctr; input wire [0:0] i_bus_busy; -input wire [0:0] i_alu_busy; input wire [0:0] i_exec_unit_busy; input wire [3:0] i_nibble; @@ -64,7 +66,6 @@ input wire [0:0] i_jump_instr; input wire [2:0] i_jump_length; input wire [0:0] i_block_0x; input wire [0:0] i_push_pc; -input wire [0:0] i_rtn_instr; output wire [19:0] o_current_pc; output reg [0:0] o_reload_pc; @@ -91,16 +92,14 @@ wire [0:0] do_jump_instr = !just_reset && i_jump_instr; reg [0:0] just_reset; reg [2:0] init_counter; reg [0:0] jump_decode; -reg [0:0] jump_exec; reg [2:0] jump_counter; reg [19:0] jump_base; -reg [19:0] jump_offset; -reg [19:0] jump_rel_addr; +reg [15:0] jump_offset; wire [0:0] jump_rel2 = i_jump_instr && (i_jump_length == 3'd1); wire [0:0] jump_rel3 = i_jump_instr && (i_jump_length == 3'd2); wire [0:0] jump_rel4 = i_jump_instr && (i_jump_length == 3'd3); -wire [0:0] jump_abs5 = i_jump_instr && (i_jump_length == 3'd4); +//wire [0:0] jump_abs5 = i_jump_instr && (i_jump_length == 3'd4); wire [0:0] jump_relative = jump_rel2 || jump_rel3 || jump_rel4; /* this appears to be SLOW */ @@ -135,7 +134,6 @@ initial begin just_reset = 1'b1; init_counter = 3'd0; jump_decode = 1'b0; - jump_exec = 1'b0; jump_counter = 3'd0; reg_PC = 20'h00000; reg_rstk_ptr = 3'd7; @@ -143,7 +141,6 @@ initial begin addr_to_return_to = 20'b0; rstk_ptr_after_pop = 3'd0; rstk_ptr_to_push_at = 3'd0; - jump_rel_addr = 20'b0; end /* @@ -210,7 +207,7 @@ always @(posedge i_clk) begin /* one step of the calculation (one nibble of data came in) */ if (i_phases[2] && do_jump_instr && jump_decode) begin $display("PC_RSTK %0d: [%d] decode jump %0d/%0d %h %5h", i_phase, i_cycle_ctr, i_jump_length, jump_counter, i_nibble, jump_next_offset); - jump_offset <= jump_next_offset; + jump_offset <= jump_next_offset[15:0]; jump_counter <= jump_counter + 3'd1; if (jump_counter == i_jump_length) begin $write("PC_RSTK %0d: [%d] execute jump(%0d) jump_base %h jump_next_offset %h", i_phase, i_cycle_ctr, i_jump_length, jump_base, jump_next_offset); @@ -258,26 +255,15 @@ always @(posedge i_clk) begin end - - // if (i_phases[0] && i_clk_en) begin - // $write("RSTK : ptr %0d | ", reg_rstk_ptr); - // for (tmp_ctr = 4'd0; tmp_ctr < 4'd8; tmp_ctr = tmp_ctr + 4'd1) - // $write("%0d => %5h | ", tmp_ctr, reg_RSTK[tmp_ctr]); - // $write("\n"); - // end - if (i_reset) begin o_reload_pc <= 1'b0; just_reset <= 1'b1; init_counter <= 3'd0; jump_decode <= 1'b0; - jump_exec <= 1'b0; jump_counter <= 3'd0; reg_PC <= 20'h00000; reg_rstk_ptr <= 3'd7; end end -reg [3:0] tmp_ctr; - endmodule \ No newline at end of file diff --git a/saturn_top.v b/saturn_top.v index 9168024..c705547 100644 --- a/saturn_top.v +++ b/saturn_top.v @@ -112,6 +112,10 @@ output reg [7:0] led; output wire [0:0] wifi_gpio0; output wire [0:0] ftdi_rxd; +// Verilator lint_off UNUSED +wire [4:0] unused = { btn[6:2] }; +// Verilator lint_on UNUSED + /* this is necessary, otherwise, the esp32 module reboots the fpga in passthrough */ assign wifi_gpio0 = btn[0]; @@ -140,16 +144,23 @@ saturn_serial serial_port ( ); reg [25:0] delay; -reg [0:0] clk2; reg [0:0] clk_en; reg [0:0] reset; wire [0:0] halt; wire [1:0] phase; + +// Verilator lint_off UNUSED wire [31:0] cycle_ctr; +// Verilator lint_on UNUSED + wire [0:0] instr_decoded; wire [0:0] debug_cycle; wire [7:0] char_to_send; + +// Verilator lint_off UNUSED wire [9:0] char_counter; +// Verilator lint_on UNUSED + wire [0:0] char_valid; wire [0:0] char_send; wire [0:0] serial_busy; @@ -175,7 +186,6 @@ initial begin led = 8'h00; delay = `DELAY_START; reset = 1'b1; - clk2 = 1'b0; end always @(posedge clk_25mhz) begin