mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-26 09:58:09 +01:00
372 lines
No EOL
12 KiB
Verilog
372 lines
No EOL
12 KiB
Verilog
/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`default_nettype none
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`include "saturn_def_buscmd.v"
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module saturn_hp48gx_sysram (
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i_clk,
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i_clk_en,
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i_reset,
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i_phase,
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i_phases,
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i_cycle_ctr,
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i_debug_cycle,
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i_bus_clk_en,
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i_bus_is_data,
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o_bus_nibble_out,
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i_bus_nibble_in,
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i_bus_daisy,
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o_bus_daisy,
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o_bus_active
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_clk_en;
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input wire [0:0] i_reset;
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input wire [1:0] i_phase;
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input wire [3:0] i_phases;
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input wire [31:0] i_cycle_ctr;
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input wire [0:0] i_debug_cycle;
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/**************************************************************************************************
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*
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* bus I/O
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*
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*************************************************************************************************/
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input wire [0:0] i_bus_clk_en;
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input wire [0:0] i_bus_is_data;
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output reg [3:0] o_bus_nibble_out;
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input wire [3:0] i_bus_nibble_in;
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input wire [0:0] i_bus_daisy;
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output wire [0:0] o_bus_daisy;
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output wire [0:0] o_bus_active;
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/**************************************************************************************************
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*
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* address handling
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*
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*************************************************************************************************/
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`define SYSRAM_BITS 18
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reg [3:0] sysram_data[0:(2** `SYSRAM_BITS) - 1];
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reg [3:0] last_cmd;
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reg [2:0] addr_pos_ctr;
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reg [19:0] local_pc;
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reg [19:0] local_dp;
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reg [0:0] pc_active;
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reg [0:0] dp_active;
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reg [0:0] base_conf;
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reg [0:0] length_conf;
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reg [19:0] base_addr;
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reg [19:0] length;
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initial begin
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last_cmd = 4'b0;
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addr_pos_ctr = 3'b0;
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local_pc = 20'b0;
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local_dp = 20'b0;
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pc_active = 1'b0;
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dp_active = 1'b0;
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base_conf = 1'b0;
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length_conf = 1'b0;
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base_addr = 20'b0;
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length = 20'b0;
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end
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/*
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* testing for read
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*/
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wire [0:0] do_pc_read = (last_cmd == `BUSCMD_PC_READ);
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wire [0:0] do_dp_read = (last_cmd == `BUSCMD_DP_READ);
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wire [0:0] do_read = do_pc_read || do_dp_read;
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/*
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* testing for write
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*/
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wire [0:0] do_pc_write = (last_cmd == `BUSCMD_PC_WRITE);
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wire [0:0] do_dp_write = (last_cmd == `BUSCMD_DP_WRITE);
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wire [0:0] do_write = do_pc_write || do_dp_write;
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/*
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* accessing the ioram
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*/
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wire [0:0] configured = length_conf && base_conf;
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assign o_bus_daisy = configured;
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wire [0:0] use_pc = do_pc_read || do_pc_write;
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wire [0:0] use_dp = do_dp_read || do_dp_write;
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wire [19:0] above_addr = base_addr + length;
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wire [0:0] active = ((pc_active && use_pc) || (dp_active && use_dp)) && configured;
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assign o_bus_active = active;
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wire [19:0] pointer = use_pc?local_pc:local_dp;
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wire [19:0] access_pointer = pointer - base_addr;
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wire [`SYSRAM_BITS-1:0] address = access_pointer[`SYSRAM_BITS-1:0];
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wire [0:0] gen_active = i_clk_en && !i_debug_cycle && i_phases[0] && (do_read || do_write);
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wire [0:0] can_read = i_bus_clk_en && i_clk_en && i_bus_is_data && do_read && configured && active;
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wire [0:0] can_write = i_bus_clk_en && i_clk_en && i_bus_is_data && do_write && configured && active;
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/*
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* reading and writing to I/O registers
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*/
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/*
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* generate the active signals
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* these comparisons incur important delays
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*/
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always @(posedge i_clk) begin
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if (gen_active) begin
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pc_active <= (local_pc >= base_addr) && (local_pc < above_addr);
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dp_active <= (local_dp >= base_addr) && (local_dp < above_addr);
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end
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if (i_reset) begin
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pc_active <= 1'b0;
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dp_active <= 1'b0;
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end
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end
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always @(posedge i_clk) begin
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if (can_read)
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o_bus_nibble_out <= sysram_data[address];
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end
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always @(posedge i_clk) begin
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if (can_write) begin
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sysram_data[address] <= i_bus_nibble_in;
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end
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end
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`ifdef SIM
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wire [3:0] imm_nibble = sysram_data[address];
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`endif
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/* generate length */
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reg [19:0] new_length;
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always @(*) begin
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case (addr_pos_ctr)
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3'd0: new_length = { 16'b0, i_bus_nibble_in };
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3'd1: new_length = { 12'b0, i_bus_nibble_in, length[ 3:0] };
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3'd2: new_length = { 8'b0, i_bus_nibble_in, length[ 7:0] };
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3'd3: new_length = { 4'b0, i_bus_nibble_in, length[11:0] };
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3'd4: new_length = { i_bus_nibble_in, length[15:0] };
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default: new_length = 20'b0;
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endcase
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end
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/* generate length */
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reg [19:0] new_base_addr;
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always @(*) begin
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case (addr_pos_ctr)
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3'd0: new_base_addr = { 16'b0, i_bus_nibble_in };
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3'd1: new_base_addr = { 12'b0, i_bus_nibble_in, base_addr[ 3:0] };
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3'd2: new_base_addr = { 8'b0, i_bus_nibble_in, base_addr[ 7:0] };
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3'd3: new_base_addr = { 4'b0, i_bus_nibble_in, base_addr[11:0] };
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3'd4: new_base_addr = { i_bus_nibble_in, base_addr[15:0] };
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default: new_base_addr = 20'b0;
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endcase
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end
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/*
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* general case
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*/
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always @(posedge i_clk) begin
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if (i_bus_clk_en && i_clk_en) begin
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if (i_bus_is_data) begin
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/* do things with the bits...*/
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case (last_cmd)
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`BUSCMD_PC_READ:
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begin
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// o_bus_nibble_out <= rom_data[local_pc[`ROMBITS-1:0]];
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local_pc <= local_pc + 1;
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end
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`BUSCMD_DP_READ:
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begin
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// o_bus_nibble_out <= rom_data[local_dp[`ROMBITS-1:0]];
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local_dp <= local_dp + 1;
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end
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`BUSCMD_PC_WRITE: local_pc <= local_pc + 1;
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`BUSCMD_DP_WRITE: local_dp <= local_dp + 1;
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`BUSCMD_LOAD_PC:
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begin
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local_pc[addr_pos_ctr*4+:4] <= i_bus_nibble_in;
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addr_pos_ctr <= addr_pos_ctr + 3'd1;
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end
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`BUSCMD_LOAD_DP:
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begin
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local_dp[addr_pos_ctr*4+:4] <= i_bus_nibble_in;
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addr_pos_ctr <= addr_pos_ctr + 3'd1;
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end
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`BUSCMD_CONFIGURE:
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if (i_bus_daisy) begin
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if (!length_conf && !base_conf) length <= new_length;
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if (length_conf && !base_conf) base_addr <= new_base_addr;
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addr_pos_ctr <= addr_pos_ctr + 3'd1;
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end
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default: begin end
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endcase
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/* auto switch to pc read / dp read */
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if (addr_pos_ctr == 4) begin
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case (last_cmd)
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`BUSCMD_LOAD_PC: last_cmd <= `BUSCMD_PC_READ;
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`BUSCMD_LOAD_DP: last_cmd <= `BUSCMD_DP_READ;
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`BUSCMD_CONFIGURE:
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begin
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if (!length_conf && !base_conf)
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begin
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length_conf <= 1'b1;
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length <= ~new_length + 20'b1;
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`ifdef SIM
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$display("RAM-GX %0d: [%d] configure length %5h => %5h", i_phase, i_cycle_ctr, new_length, ~new_length + 20'b1);
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`endif
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end
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if (length_conf && !base_conf)
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begin
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base_conf <= 1'b1;
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`ifdef SIM
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$display("RAM-GX %0d: [%d] configure base_addr %5h", i_phase, i_cycle_ctr, new_base_addr);
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`endif
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end
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end
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default: begin end
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endcase
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end
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`ifdef SIM
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$write("RAM-GX %0d: [%d] ", i_phase, i_cycle_ctr);
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case (last_cmd)
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`BUSCMD_PC_READ:
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begin
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$write("PC_READ ");
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if (configured)
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begin
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if (active) $write("<= sysram[%5h]: %h", local_pc, imm_nibble);
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else $write("inactive");
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end
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else $write("(unconfigured)");
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end
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`BUSCMD_DP_READ:
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begin
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$write("DP_READ ");
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if (configured)
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begin
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if (active) $write("<= sysram[%5h]: %h", local_dp, imm_nibble);
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else $write("(inactive)");
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end
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else $write("(unconfigured)");
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end
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`BUSCMD_DP_WRITE:
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begin
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$write("DP_WRITE ");
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if (configured)
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begin
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if (active) $write("sysram[%5h] <= %h", local_dp, i_bus_nibble_in);
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else $write("(inactive %h)", i_bus_nibble_in);
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end
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else $write("(ignore)");
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end
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`BUSCMD_LOAD_PC: $write("LOAD_PC - pc %5h, %h pos %0d", local_pc, i_bus_nibble_in, addr_pos_ctr);
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`BUSCMD_LOAD_DP: $write("LOAD_DP - dp %5h, %h pos %0d", local_dp, i_bus_nibble_in, addr_pos_ctr);
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`BUSCMD_CONFIGURE:
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begin
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$write("CONFIGURE - ");
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if (!configured)
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begin
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if (!length_conf) $write("length %5h", new_length);
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else $write("base_addr %5h", new_base_addr);
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$write(", %h pos %0d", i_bus_nibble_in, addr_pos_ctr);
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end
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else $write("already done, ignore");
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end
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`BUSCMD_RESET: $write("RESET");
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default: $write("last_command %h nibble %h - UNHANDLED", last_cmd, i_bus_nibble_in);
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endcase
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if (addr_pos_ctr == 4) begin
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case (last_cmd)
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`BUSCMD_LOAD_PC: $write(" auto switch to PC_READ");
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`BUSCMD_LOAD_DP: $write(" auto switch to DP_READ");
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default: begin end
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endcase
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end
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$write("\n");
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`endif
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end else begin
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last_cmd <= i_bus_nibble_in;
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if ((i_bus_nibble_in == `BUSCMD_LOAD_PC) || (i_bus_nibble_in == `BUSCMD_LOAD_DP))
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addr_pos_ctr <= 0;
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if (i_bus_nibble_in == `BUSCMD_CONFIGURE)
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addr_pos_ctr <= 3'd0;
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if (i_bus_nibble_in == `BUSCMD_RESET)
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begin
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base_addr <= 20'b0;
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base_conf <= 1'b0;
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length <= 20'b0;
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length_conf <= 1'b0;
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end
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`ifdef SIM
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$write("RAM-GX %0d: [%d] ", i_phase, i_cycle_ctr);
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case (i_bus_nibble_in)
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`BUSCMD_PC_READ: $write("PC_READ");
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`BUSCMD_DP_READ: $write("DP_READ");
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`BUSCMD_DP_WRITE: $write("DP_WRITE");
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`BUSCMD_LOAD_PC: $write("LOAD_PC");
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`BUSCMD_LOAD_DP: $write("LOAD_DP");
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`BUSCMD_CONFIGURE: $write("CONFIGURE");
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`BUSCMD_RESET: $write("RESET base_addr to %5h and unconfigure", 20'h0);
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default: begin end
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endcase
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$write("\n");
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`endif
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end
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end
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if (i_reset) begin
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last_cmd <= 4'b0;
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addr_pos_ctr <= 3'b0;
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local_pc <= 20'b0;
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local_dp <= 20'b0;
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base_addr <= 20'b0;
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end
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end
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// Verilator lint_off UNUSED
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wire [(19 -`SYSRAM_BITS):0] unused = { access_pointer[19:`SYSRAM_BITS] };
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// Verilator lint_on UNUSED
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endmodule |