2019-02-06 10:40:55 +01:00
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Verilog implementation of the HP saturn processor
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2019-02-07 08:35:59 +01:00
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licence: GPLv3 or later
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timings:
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2019-03-02 17:06:23 +01:00
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```
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2019-02-11 19:24:57 +01:00
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___________
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reset: |____________________________________________________
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____ ____ ____ ____ ____ ____
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clk : ____| |____| |____| |____| |____| |____| |____
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_________ _________ _________ _________ _________
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counter: ______________/____0____X____1____X____2____X____3____X____0____
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_________ _________
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phase_0: ______________| |_____________________________|
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2019-02-11 16:58:15 +01:00
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_________
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2019-02-11 19:24:57 +01:00
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phase_1: ________________________| |_____________________________
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2019-02-11 16:58:15 +01:00
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_________
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2019-02-11 19:24:57 +01:00
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phase_2: __________________________________| |___________________
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_________
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2019-02-14 22:14:52 +01:00
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phase_3: ____________________________________________| |_________
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2019-03-02 17:06:23 +01:00
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```
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