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fix bug inside mmu for div reset register

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Colby 2016-07-18 21:07:18 +10:00
parent 5e6aa1391c
commit f5c9376663
1 changed files with 1 additions and 1 deletions
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lib/waterfoul/mmu.rb
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@ -73,7 +73,7 @@ module Waterfoul
when 0xFF46 # DMA transfer
dma_transfer v
when 0xFF04 # reset divider register
self[i] = 0
@memory[i] = 0
else
@memory[i] = v
end