From f5c9376663dd67f0fbb5d887b4d8fc7e07efeb04 Mon Sep 17 00:00:00 2001
From: Colby <colby@taplaboratories.com.au>
Date: Mon, 18 Jul 2016 21:07:18 +1000
Subject: [PATCH] fix bug inside mmu for div reset register

---
 lib/waterfoul/mmu.rb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/waterfoul/mmu.rb b/lib/waterfoul/mmu.rb
index 84a03cc..863118d 100644
--- a/lib/waterfoul/mmu.rb
+++ b/lib/waterfoul/mmu.rb
@@ -73,7 +73,7 @@ module Waterfoul
         when 0xFF46 # DMA transfer
           dma_transfer v
         when 0xFF04 # reset divider register
-          self[i] = 0
+          @memory[i] = 0
         else
           @memory[i] = v
         end