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Signed-off-by: B. Watson <yalhcru@gmail.com> Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org>
6 lines
385 B
Text
6 lines
385 B
Text
Icarus Verilog is a Verilog simulation and synthesis tool. It operates
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as a compiler, compiling source code written in Verilog (IEEE-1364)
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into some target format. For batch simulation, the compiler can
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generate an intermediate form called vvp assembly. This intermediate
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form is executed by the 'vvp' command. For synthesis, the compiler
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generates netlists in the desired format.
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