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academic/verilog: Fix README.

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Signed-off-by: B. Watson <yalhcru@gmail.com>

Signed-off-by: Willy Sudiarto Raharjo <willysr@slackbuilds.org>
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B. Watson 2020-10-12 15:12:21 -04:00 committed by Willy Sudiarto Raharjo
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academic/verilog/README
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Icarus Verilog is a Verilog simulation and synthesis tool. It operates as
a compiler, compiling source code written in Verilog (IEEE-1364) into some
target format. For batch simulation, the compiler can generate an intermediate
form called vvp assembly. This intermediate form is executed by the 'vvp'
command. For synthesis, the compiler generates netlists in the desired format.
Icarus Verilog is a Verilog simulation and synthesis tool. It operates
as a compiler, compiling source code written in Verilog (IEEE-1364)
into some target format. For batch simulation, the compiler can
generate an intermediate form called vvp assembly. This intermediate
form is executed by the 'vvp' command. For synthesis, the compiler
generates netlists in the desired format.