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https://github.com/mamedev/mame.git
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atlantis: added PCI9050 device skeleton. [R. Belmont]
This commit is contained in:
arbee
parent
7977b2a8f6
commit
b96b59caee
5 changed files with 240 additions and 1 deletions
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@ -2637,3 +2637,16 @@ if (MACHINES["FDC37C665GT"]~=null) then
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MAME_DIR .. "src/emu/machine/fdc37c665gt.h",
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}
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end
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---------------------------------------------------
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--
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--@src/emu/machine/pci9050.h,MACHINES += PCI9050
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---------------------------------------------------
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if (MACHINES["PCI9050"]~=null) then
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files {
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MAME_DIR .. "src/emu/machine/pci9050.c",
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MAME_DIR .. "src/emu/machine/pci9050.h",
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}
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end
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@ -554,6 +554,7 @@ MACHINES["STEPPERS"] = true
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--MACHINES["CORVUSHD"] = true
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--MACHINES["WOZFDC"] = true
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--MACHINES["DIABLO_HD"] = true
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MACHINES["PCI9050"] = true
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--------------------------------------------------
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-- specify available bus cores
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181
src/emu/machine/pci9050.c
Normal file
181
src/emu/machine/pci9050.c
Normal file
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@ -0,0 +1,181 @@
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/*********************************************************************
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pci9050.c - PLX PCI9050 PCI to 4x Local Bus Bridge
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by R. Belmont
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PCI spaces:
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0 - (config memory) not used
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1 - (config I/O) config regs
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2 - local bus 1 window
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3 - local bus 2 window
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4 - local bus 3 window
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5 - local bus 4 window
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PCI9050 is located, mapped, and initialized at BFC00700.
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The boot ROM then copies ROM to RAM, jumps to RAM, and starts trying to
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access Zeus 2 video through the mapped windows.
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*********************************************************************/
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#include "pci9050.h"
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const device_type PCI9050 = &device_creator<pci9050_device>;
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DEVICE_ADDRESS_MAP_START(map, 32, pci9050_device)
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AM_RANGE(0x00, 0x5f) AM_READWRITE(reg_r, reg_w)
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ADDRESS_MAP_END
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pci9050_device::pci9050_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: pci_device(mconfig, PCI9050, "PLX PCI9050 PCI to Local Bus Bridge", tag, owner, clock, "pci9050", __FILE__)
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{
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}
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enum
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{
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CFG_LS0_RANGE = 0,
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CFG_LS1_RANGE,
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CFG_LS2_RANGE,
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CFG_LS3_RANGE,
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CFG_ROM_RANGE,
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CFG_LS0_BASE,
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CFG_LS1_BASE,
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CFG_LS2_BASE,
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CFG_LS3_BASE,
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CFG_ROM_BASE,
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CFG_LS0_DESCRIPTORS,
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CFG_LS1_DESCRIPTORS,
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CFG_LS2_DESCRIPTORS,
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CFG_LS3_DESCRIPTORS,
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CFG_ROM_DESCRIPTORS,
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CFG_CS0_BASE,
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CFG_CS1_BASE,
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CFG_CS2_BASE,
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CFG_CS3_BASE,
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CFG_IRQ_CTRL_STATUS,
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CFG_MISC_CTRL
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};
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void pci9050_device::device_start()
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{
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pci_device::device_start();
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skip_map_regs(1); // we don't use map 0
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add_map(0x60, M_IO, FUNC(pci9050_device::map)); // map 1 is our config registers
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}
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void pci9050_device::device_config_complete()
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{
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}
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void pci9050_device::device_reset()
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{
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pci_device::device_reset();
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}
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READ32_MEMBER (pci9050_device::reg_r)
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{
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UINT32 result = m_regs[offset];
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logerror("%06X:PCI9050 read from reg %02x = %08x (mask %08x)\n", space.device().safe_pc(), offset*4, result, mem_mask);
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return result;
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}
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WRITE32_MEMBER(pci9050_device::reg_w)
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{
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m_regs[offset] = data;
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switch (offset)
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{
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case CFG_LS0_RANGE:
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logerror("%06X:PCI9050 local bus 0 range %08x: %s flags %d pf %d addr bits 27-4 %08x\n", space.device().safe_pc(), data, (data & 1) ? "I/O" : "MEM", (data & 6)>>1, (data & 8)>>3, data & 0xfffffff);
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break;
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case CFG_LS1_RANGE:
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logerror("%06X:PCI9050 local bus 1 range %08x: %s flags %d pf %d addr bits 27-4 %08x\n", space.device().safe_pc(), data, (data & 1) ? "I/O" : "MEM", (data & 6)>>1, (data & 8)>>3, data & 0xfffffff);
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break;
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case CFG_LS2_RANGE:
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logerror("%06X:PCI9050 local bus 2 range %08x: %s flags %d pf %d addr bits 27-4 %08x\n", space.device().safe_pc(), data, (data & 1) ? "I/O" : "MEM", (data & 6)>>1, (data & 8)>>3, data & 0xfffffff);
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break;
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case CFG_LS3_RANGE:
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logerror("%06X:PCI9050 local bus 3 range %08x: %s flags %d pf %d addr bits 27-4 %08x\n", space.device().safe_pc(), data, (data & 1) ? "I/O" : "MEM", (data & 6)>>1, (data & 8)>>3, data & 0xfffffff);
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break;
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case CFG_ROM_RANGE:
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logerror("%06X:PCI9050 ROM range %08x: addr bits 27-11 %08x\n", space.device().safe_pc(), data, data & 0xfffff800);
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break;
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case CFG_LS0_BASE:
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logerror("%06X:PCI9050 local bus 0 base %08x: enable %d remap %08x\n", space.device().safe_pc(), data, data&1, data & 0x0ffffffe);
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break;
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case CFG_LS1_BASE:
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logerror("%06X:PCI9050 local bus 1 base %08x: enable %d remap %08x\n", space.device().safe_pc(), data, data&1, data & 0x0ffffffe);
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break;
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case CFG_LS2_BASE:
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logerror("%06X:PCI9050 local bus 2 base %08x: enable %d remap %08x\n", space.device().safe_pc(), data, data&1, data & 0x0ffffffe);
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break;
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case CFG_LS3_BASE:
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logerror("%06X:PCI9050 local bus 3 base %08x: enable %d remap %08x\n", space.device().safe_pc(), data, data&1, data & 0x0ffffffe);
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break;
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case CFG_ROM_BASE:
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logerror("%06X:PCI9050 ROM base %08x: remap %08x\n", space.device().safe_pc(), data, data & 0x0ffff800);
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break;
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case CFG_LS0_DESCRIPTORS:
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logerror("%06X:PCI9050 local bus 0 descriptors %08x: burst %d prefetch %d width %d, endian %s, endian mode %d\n", space.device().safe_pc(), data, data&1, (data >> 5) & 1, (data >> 22) & 3, ((data >> 24) & 1) ? "BE" : "LE", (data >> 25) & 1);
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break;
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case CFG_LS1_DESCRIPTORS:
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logerror("%06X:PCI9050 local bus 1 descriptors %08x: burst %d prefetch %d width %d, endian %s, endian mode %d\n", space.device().safe_pc(), data, data&1, (data >> 5) & 1, (data >> 22) & 3, ((data >> 24) & 1) ? "BE" : "LE", (data >> 25) & 1);
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break;
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case CFG_LS2_DESCRIPTORS:
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logerror("%06X:PCI9050 local bus 2 descriptors %08x: burst %d prefetch %d width %d, endian %s, endian mode %d\n", space.device().safe_pc(), data, data&1, (data >> 5) & 1, (data >> 22) & 3, ((data >> 24) & 1) ? "BE" : "LE", (data >> 25) & 1);
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break;
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case CFG_LS3_DESCRIPTORS:
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logerror("%06X:PCI9050 local bus 3 descriptors %08x: burst %d prefetch %d width %d, endian %s, endian mode %d\n", space.device().safe_pc(), data, data&1, (data >> 5) & 1, (data >> 22) & 3, ((data >> 24) & 1) ? "BE" : "LE", (data >> 25) & 1);
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break;
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case CFG_ROM_DESCRIPTORS:
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logerror("%06X:PCI9050 ROM descriptors %08x: burst %d prefetch %d bits %d, endian %s, endian mode %d\n", space.device().safe_pc(), data, data&1, (data >> 5) & 1, (data >> 22) & 3, ((data >> 24) & 1) ? "BE" : "LE", (data >> 25) & 1);
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break;
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case CFG_CS0_BASE:
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logerror("%06X:PCI9050 chip select 0 base %08x: enable %d size %08x\n", space.device().safe_pc(), data, data&1, data&0xfffffffe);
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break;
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case CFG_CS1_BASE:
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logerror("%06X:PCI9050 chip select 1 base %08x: enable %d size %08x\n", space.device().safe_pc(), data, data&1, data&0xfffffffe);
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break;
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case CFG_CS2_BASE:
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logerror("%06X:PCI9050 chip select 2 base %08x: enable %d size %08x\n", space.device().safe_pc(), data, data&1, data&0xfffffffe);
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break;
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case CFG_CS3_BASE:
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logerror("%06X:PCI9050 chip select 3 base %08x: enable %d size %08x\n", space.device().safe_pc(), data, data&1, data&0xfffffffe);
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break;
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case CFG_IRQ_CTRL_STATUS:
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logerror("%06X:PCI9050 IRQ control %08x\n", space.device().safe_pc(), data);
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break;
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case CFG_MISC_CTRL:
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logerror("%06X:PCI9050 misc control %08x\n", space.device().safe_pc(), data);
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break;
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default:
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logerror("%06X:PCI9050 write to offset %02x = %08x (mask %08x)\n", space.device().safe_pc(), offset*4, data, mem_mask);
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break;
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}
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}
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43
src/emu/machine/pci9050.h
Normal file
43
src/emu/machine/pci9050.h
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@ -0,0 +1,43 @@
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/*********************************************************************
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pci9050.h - PLX PCI9050 PCI to 4x Local Bus Bridge
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by R. Belmont
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*********************************************************************/
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#ifndef _PCI9050_H
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#define _PCI9050_H
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#include "machine/pci.h"
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#define MCFG_PCI9050_ADD(_tag) \
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MCFG_PCI_DEVICE_ADD(_tag, PCI9050, 0x10b59050, 0x01, 0x06800000, 0x10b59050)
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class pci9050_device :
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public pci_device
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{
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public:
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pci9050_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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// PCI9050 I/O register space handlers
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DECLARE_READ32_MEMBER(reg_r);
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DECLARE_WRITE32_MEMBER(reg_w);
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protected:
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virtual void device_start();
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virtual void device_config_complete();
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virtual void device_reset();
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private:
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DECLARE_ADDRESS_MAP(map, 32);
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address_space_config m_as0_config, m_as1_config, m_as2_config, m_as3_config;
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address_space *m_as0, *m_as1, *m_as2, *m_as3;
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UINT32 m_regs[0x54/4];
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};
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extern const device_type PCI9050;
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#endif
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@ -38,7 +38,7 @@
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#include "audio/dcs.h"
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#include "machine/pci.h"
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#include "machine/vrc4373.h"
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#include "machine/pci9050.h"
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class atlantis_state : public driver_device
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{
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@ -128,6 +128,7 @@ static MACHINE_CONFIG_START( mwskins, atlantis_state )
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MCFG_PCI_ROOT_ADD( ":pci")
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MCFG_VRC4373_ADD( ":pci:00.0", ":maincpu")
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MCFG_PCI9050_ADD( ":pci:0b.0")
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MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)
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