From b96b59caee24b5385e0fce1900c5cce956e76c8d Mon Sep 17 00:00:00 2001 From: arbee Date: Sun, 12 Apr 2015 13:13:33 -0400 Subject: [PATCH] atlantis: added PCI9050 device skeleton. [R. Belmont] --- scripts/src/machine.lua | 13 +++ scripts/target/mame/mame.lua | 1 + src/emu/machine/pci9050.c | 181 +++++++++++++++++++++++++++++++++++ src/emu/machine/pci9050.h | 43 +++++++++ src/mame/drivers/atlantis.c | 3 +- 5 files changed, 240 insertions(+), 1 deletion(-) create mode 100644 src/emu/machine/pci9050.c create mode 100644 src/emu/machine/pci9050.h diff --git a/scripts/src/machine.lua b/scripts/src/machine.lua index 9f0d7d4406f..e9691eb19b2 100644 --- a/scripts/src/machine.lua +++ b/scripts/src/machine.lua @@ -2637,3 +2637,16 @@ if (MACHINES["FDC37C665GT"]~=null) then MAME_DIR .. "src/emu/machine/fdc37c665gt.h", } end + +--------------------------------------------------- +-- +--@src/emu/machine/pci9050.h,MACHINES += PCI9050 +--------------------------------------------------- + +if (MACHINES["PCI9050"]~=null) then + files { + MAME_DIR .. "src/emu/machine/pci9050.c", + MAME_DIR .. "src/emu/machine/pci9050.h", + } +end + diff --git a/scripts/target/mame/mame.lua b/scripts/target/mame/mame.lua index 09361d7902b..ed4f2eda6f8 100644 --- a/scripts/target/mame/mame.lua +++ b/scripts/target/mame/mame.lua @@ -554,6 +554,7 @@ MACHINES["STEPPERS"] = true --MACHINES["CORVUSHD"] = true --MACHINES["WOZFDC"] = true --MACHINES["DIABLO_HD"] = true +MACHINES["PCI9050"] = true -------------------------------------------------- -- specify available bus cores diff --git a/src/emu/machine/pci9050.c b/src/emu/machine/pci9050.c new file mode 100644 index 00000000000..4ca85648e27 --- /dev/null +++ b/src/emu/machine/pci9050.c @@ -0,0 +1,181 @@ +/********************************************************************* + + pci9050.c - PLX PCI9050 PCI to 4x Local Bus Bridge + + by R. Belmont + + PCI spaces: + 0 - (config memory) not used + 1 - (config I/O) config regs + 2 - local bus 1 window + 3 - local bus 2 window + 4 - local bus 3 window + 5 - local bus 4 window + + PCI9050 is located, mapped, and initialized at BFC00700. + + The boot ROM then copies ROM to RAM, jumps to RAM, and starts trying to + access Zeus 2 video through the mapped windows. + +*********************************************************************/ + +#include "pci9050.h" + +const device_type PCI9050 = &device_creator; + +DEVICE_ADDRESS_MAP_START(map, 32, pci9050_device) + AM_RANGE(0x00, 0x5f) AM_READWRITE(reg_r, reg_w) +ADDRESS_MAP_END + +pci9050_device::pci9050_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : pci_device(mconfig, PCI9050, "PLX PCI9050 PCI to Local Bus Bridge", tag, owner, clock, "pci9050", __FILE__) +{ +} + +enum +{ + CFG_LS0_RANGE = 0, + CFG_LS1_RANGE, + CFG_LS2_RANGE, + CFG_LS3_RANGE, + CFG_ROM_RANGE, + CFG_LS0_BASE, + CFG_LS1_BASE, + CFG_LS2_BASE, + CFG_LS3_BASE, + CFG_ROM_BASE, + CFG_LS0_DESCRIPTORS, + CFG_LS1_DESCRIPTORS, + CFG_LS2_DESCRIPTORS, + CFG_LS3_DESCRIPTORS, + CFG_ROM_DESCRIPTORS, + CFG_CS0_BASE, + CFG_CS1_BASE, + CFG_CS2_BASE, + CFG_CS3_BASE, + CFG_IRQ_CTRL_STATUS, + CFG_MISC_CTRL +}; + +void pci9050_device::device_start() +{ + pci_device::device_start(); + + skip_map_regs(1); // we don't use map 0 + add_map(0x60, M_IO, FUNC(pci9050_device::map)); // map 1 is our config registers +} + +void pci9050_device::device_config_complete() +{ +} + +void pci9050_device::device_reset() +{ + pci_device::device_reset(); +} + +READ32_MEMBER (pci9050_device::reg_r) +{ + UINT32 result = m_regs[offset]; + + logerror("%06X:PCI9050 read from reg %02x = %08x (mask %08x)\n", space.device().safe_pc(), offset*4, result, mem_mask); + + return result; +} + +WRITE32_MEMBER(pci9050_device::reg_w) +{ + m_regs[offset] = data; + + switch (offset) + { + case CFG_LS0_RANGE: + logerror("%06X:PCI9050 local bus 0 range %08x: %s flags %d pf %d addr bits 27-4 %08x\n", space.device().safe_pc(), data, (data & 1) ? "I/O" : "MEM", (data & 6)>>1, (data & 8)>>3, data & 0xfffffff); + break; + + case CFG_LS1_RANGE: + logerror("%06X:PCI9050 local bus 1 range %08x: %s flags %d pf %d addr bits 27-4 %08x\n", space.device().safe_pc(), data, (data & 1) ? "I/O" : "MEM", (data & 6)>>1, (data & 8)>>3, data & 0xfffffff); + break; + + case CFG_LS2_RANGE: + logerror("%06X:PCI9050 local bus 2 range %08x: %s flags %d pf %d addr bits 27-4 %08x\n", space.device().safe_pc(), data, (data & 1) ? "I/O" : "MEM", (data & 6)>>1, (data & 8)>>3, data & 0xfffffff); + break; + + case CFG_LS3_RANGE: + logerror("%06X:PCI9050 local bus 3 range %08x: %s flags %d pf %d addr bits 27-4 %08x\n", space.device().safe_pc(), data, (data & 1) ? "I/O" : "MEM", (data & 6)>>1, (data & 8)>>3, data & 0xfffffff); + break; + + case CFG_ROM_RANGE: + logerror("%06X:PCI9050 ROM range %08x: addr bits 27-11 %08x\n", space.device().safe_pc(), data, data & 0xfffff800); + break; + + case CFG_LS0_BASE: + logerror("%06X:PCI9050 local bus 0 base %08x: enable %d remap %08x\n", space.device().safe_pc(), data, data&1, data & 0x0ffffffe); + break; + + case CFG_LS1_BASE: + logerror("%06X:PCI9050 local bus 1 base %08x: enable %d remap %08x\n", space.device().safe_pc(), data, data&1, data & 0x0ffffffe); + break; + + case CFG_LS2_BASE: + logerror("%06X:PCI9050 local bus 2 base %08x: enable %d remap %08x\n", space.device().safe_pc(), data, data&1, data & 0x0ffffffe); + break; + + case CFG_LS3_BASE: + logerror("%06X:PCI9050 local bus 3 base %08x: enable %d remap %08x\n", space.device().safe_pc(), data, data&1, data & 0x0ffffffe); + break; + + case CFG_ROM_BASE: + logerror("%06X:PCI9050 ROM base %08x: remap %08x\n", space.device().safe_pc(), data, data & 0x0ffff800); + break; + + case CFG_LS0_DESCRIPTORS: + logerror("%06X:PCI9050 local bus 0 descriptors %08x: burst %d prefetch %d width %d, endian %s, endian mode %d\n", space.device().safe_pc(), data, data&1, (data >> 5) & 1, (data >> 22) & 3, ((data >> 24) & 1) ? "BE" : "LE", (data >> 25) & 1); + break; + + case CFG_LS1_DESCRIPTORS: + logerror("%06X:PCI9050 local bus 1 descriptors %08x: burst %d prefetch %d width %d, endian %s, endian mode %d\n", space.device().safe_pc(), data, data&1, (data >> 5) & 1, (data >> 22) & 3, ((data >> 24) & 1) ? "BE" : "LE", (data >> 25) & 1); + break; + + case CFG_LS2_DESCRIPTORS: + logerror("%06X:PCI9050 local bus 2 descriptors %08x: burst %d prefetch %d width %d, endian %s, endian mode %d\n", space.device().safe_pc(), data, data&1, (data >> 5) & 1, (data >> 22) & 3, ((data >> 24) & 1) ? "BE" : "LE", (data >> 25) & 1); + break; + + case CFG_LS3_DESCRIPTORS: + logerror("%06X:PCI9050 local bus 3 descriptors %08x: burst %d prefetch %d width %d, endian %s, endian mode %d\n", space.device().safe_pc(), data, data&1, (data >> 5) & 1, (data >> 22) & 3, ((data >> 24) & 1) ? "BE" : "LE", (data >> 25) & 1); + break; + + case CFG_ROM_DESCRIPTORS: + logerror("%06X:PCI9050 ROM descriptors %08x: burst %d prefetch %d bits %d, endian %s, endian mode %d\n", space.device().safe_pc(), data, data&1, (data >> 5) & 1, (data >> 22) & 3, ((data >> 24) & 1) ? "BE" : "LE", (data >> 25) & 1); + break; + + case CFG_CS0_BASE: + logerror("%06X:PCI9050 chip select 0 base %08x: enable %d size %08x\n", space.device().safe_pc(), data, data&1, data&0xfffffffe); + break; + + case CFG_CS1_BASE: + logerror("%06X:PCI9050 chip select 1 base %08x: enable %d size %08x\n", space.device().safe_pc(), data, data&1, data&0xfffffffe); + break; + + case CFG_CS2_BASE: + logerror("%06X:PCI9050 chip select 2 base %08x: enable %d size %08x\n", space.device().safe_pc(), data, data&1, data&0xfffffffe); + break; + + case CFG_CS3_BASE: + logerror("%06X:PCI9050 chip select 3 base %08x: enable %d size %08x\n", space.device().safe_pc(), data, data&1, data&0xfffffffe); + break; + + case CFG_IRQ_CTRL_STATUS: + logerror("%06X:PCI9050 IRQ control %08x\n", space.device().safe_pc(), data); + break; + + case CFG_MISC_CTRL: + logerror("%06X:PCI9050 misc control %08x\n", space.device().safe_pc(), data); + break; + + default: + logerror("%06X:PCI9050 write to offset %02x = %08x (mask %08x)\n", space.device().safe_pc(), offset*4, data, mem_mask); + break; + } + +} diff --git a/src/emu/machine/pci9050.h b/src/emu/machine/pci9050.h new file mode 100644 index 00000000000..eba973e7603 --- /dev/null +++ b/src/emu/machine/pci9050.h @@ -0,0 +1,43 @@ +/********************************************************************* + + pci9050.h - PLX PCI9050 PCI to 4x Local Bus Bridge + + by R. Belmont + +*********************************************************************/ + +#ifndef _PCI9050_H +#define _PCI9050_H + +#include "machine/pci.h" + +#define MCFG_PCI9050_ADD(_tag) \ + MCFG_PCI_DEVICE_ADD(_tag, PCI9050, 0x10b59050, 0x01, 0x06800000, 0x10b59050) + +class pci9050_device : + public pci_device +{ +public: + pci9050_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + + // PCI9050 I/O register space handlers + DECLARE_READ32_MEMBER(reg_r); + DECLARE_WRITE32_MEMBER(reg_w); + +protected: + virtual void device_start(); + virtual void device_config_complete(); + virtual void device_reset(); + +private: + DECLARE_ADDRESS_MAP(map, 32); + + address_space_config m_as0_config, m_as1_config, m_as2_config, m_as3_config; + address_space *m_as0, *m_as1, *m_as2, *m_as3; + + UINT32 m_regs[0x54/4]; +}; + +extern const device_type PCI9050; + +#endif diff --git a/src/mame/drivers/atlantis.c b/src/mame/drivers/atlantis.c index 803270545b6..f6753c80554 100644 --- a/src/mame/drivers/atlantis.c +++ b/src/mame/drivers/atlantis.c @@ -38,7 +38,7 @@ #include "audio/dcs.h" #include "machine/pci.h" #include "machine/vrc4373.h" - +#include "machine/pci9050.h" class atlantis_state : public driver_device { @@ -128,6 +128,7 @@ static MACHINE_CONFIG_START( mwskins, atlantis_state ) MCFG_PCI_ROOT_ADD( ":pci") MCFG_VRC4373_ADD( ":pci:00.0", ":maincpu") + MCFG_PCI9050_ADD( ":pci:0b.0") MCFG_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", NULL, true)