mirror of
https://github.com/sxpert/hp-saturn
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36 lines
802 B
Verilog
36 lines
802 B
Verilog
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/******************************************************************************
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* 80
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* a lot of things start with 80...
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*
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*/
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`include "decstates.v"
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`include "bus_commands.v"
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`DEC_80X: begin
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case (nb_in)
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4'h5: begin
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add_out <= C[19:0];
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next_cycle <= `BUSCMD_CONFIGURE;
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decstate <= `DEC_START;
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`ifdef SIM
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$display("%05h CONFIG", inst_start_PC);
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`endif
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end
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4'h8: decstate <= `DEC_808X;
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4'hA: begin
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next_cycle <= `BUSCMD_RESET;
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decstate <= `DEC_START;
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`ifdef SIM
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$display("%05h RESET", inst_start_PC);
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`endif
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end
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4'hC: decstate <= `DEC_C_EQ_P_N;
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4'hD: decstate <= `DEC_P_EQ_C_N;
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default: begin
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$display("ERROR : DEC_80X");
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decode_error <= 1;
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end
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endcase
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end
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