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https://github.com/sxpert/hp-saturn
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24 lines
531 B
Verilog
24 lines
531 B
Verilog
/******************************************************************************
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* 82x
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*
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* lots of things there
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*
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*/
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`include "decstates.v"
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`DEC_82X_CLRHST: begin
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HST <= HST & ~nibble;
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decstate <= `DEC_START;
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`ifdef SIM
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$write("%5h ", inst_start_PC);
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case (nibble)
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4'h1: $display("XM=0");
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4'h2: $display("SB=0");
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4'h4: $display("SR=0");
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4'h8: $display("MP=0");
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4'hf: $display("CLRHST");
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default: $display("CLRHST\t%f", nibble);
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endcase
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`endif
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end
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