mirror of
https://github.com/sxpert/hp-saturn
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54 lines
832 B
Verilog
54 lines
832 B
Verilog
`ifndef _SATURN_ALU
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`define _SATURN_ALU
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`include "def-alu.v"
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module saturn_alu (
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i_clk,
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i_reset,
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i_en_alu_prep,
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i_en_alu_calc,
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i_en_alu_save,
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i_field_start,
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i_field_last,
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i_alu_op,
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o_reg_p
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_reset;
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input wire [0:0] i_en_alu_prep;
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input wire [0:0] i_en_alu_calc;
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input wire [0:0] i_en_alu_save;
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input wire [3:0] i_field_start;
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input wire [3:0] i_field_last;
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input wire [4:0] i_alu_op;
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output wire [3:0] o_reg_p;
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assign o_reg_p = P;
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reg [3:0] P;
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initial begin
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P = 3;
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end
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always @(posedge i_clk) begin
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if (!i_reset) begin
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if (i_en_alu_prep) begin
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`ifdef SIM
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$display("ALU_PREP: alu_op %h | f_start %h | f_last %h", i_alu_op, i_field_start, i_field_last);
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`endif
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end
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end
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end
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endmodule
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