mirror of
https://github.com/sxpert/hp-saturn
synced 2025-01-19 10:26:58 +01:00
52 lines
1.2 KiB
Verilog
52 lines
1.2 KiB
Verilog
/******************************************************************************
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* 8
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* a lot of things start with 8...
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*
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*/
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`include "decstates.v"
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`DEC_FX: begin
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field <= `T_FIELD_A;
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alu_first <= 0;
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alu_last <= 4;
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alu_reg_dest <= reg_ABCD;
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if (!nb_in[3]) begin
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$display("F%h shifts not implemented");
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alu_debug <= 1;
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alu_halt <= 1;
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end else begin
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alu_reg_src1 <= reg_ABCD;
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alu_op <= nb_in[2]?`ALU_OP_1CMPL:`ALU_OP_2CMPL;
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end
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next_cycle <= `BUSCMD_NOP;
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decstate <= `DEC_ALU_INIT;
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alu_return <= `DEC_START;
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`ifdef SIM
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$write("%5h ", inst_start_PC);
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case ({2'b00, nb_in[1:0]})
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`ALU_REG_A: $write("A");
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`ALU_REG_B: $write("B");
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`ALU_REG_C: $write("C");
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`ALU_REG_D: $write("D");
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endcase
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if (!nb_in[3]) begin
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$write("S");
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if (!nb_in[2]) $write("L");
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else $write("R");
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end else begin
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$write("=-");
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case ({2'b00, nb_in[1:0]})
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`ALU_REG_A: $write("A");
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`ALU_REG_B: $write("B");
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`ALU_REG_C: $write("C");
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`ALU_REG_D: $write("D");
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endcase
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if (nb_in[2]) $write("-1");
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end
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$display("\tA");
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`endif
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end
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