mirror of
https://github.com/sxpert/hp-saturn
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36 lines
876 B
Verilog
36 lines
876 B
Verilog
/******************************************************************************
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* 13X
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*
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*
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*/
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`include "decstates.v"
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`DEC_13X: begin
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field <= `T_FIELD_A;
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alu_first <= 0;
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alu_last <= nb_in[3]?3:4;
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alu_reg_dest <= {1'b0, !nb_in[1], nb_in[2] && nb_in[1], !nb_in[1] && nb_in[0]};
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alu_reg_src1 <= {1'b0, nb_in[1], nb_in[2] && !nb_in[1], nb_in[1] && nb_in[0]};
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alu_op <= nb_in[1]?`ALU_OP_EXCH:`ALU_OP_COPY;
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next_cycle <= `BUSCMD_NOP;
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decstate <= `DEC_ALU_INIT;
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alu_return <= `DEC_START;
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alu_debug <= 1;
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`ifdef SIM
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$write("%5h ", inst_start_PC);
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if (!nb_in[1])
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$write("D");
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else
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$write("%sD", nb_in[3]?"C":"A");
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$write("%b", nb_in[0]);
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if (!nb_in[1])
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$write("=%s%s", nb_in[2]?"C":"A", nb_in[3]?"S":"");
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else
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$write("%s", nb_in[3]?"XS":"EX");
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$display("");
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`endif
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end
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