mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-26 09:58:09 +01:00
276 lines
No EOL
8.6 KiB
Verilog
276 lines
No EOL
8.6 KiB
Verilog
/*
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(c) Raphaël Jacquot 2019
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This file is part of hp_saturn.
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hp_saturn is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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any later version.
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hp_saturn is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with Foobar. If not, see <https://www.gnu.org/licenses/>.
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*/
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`default_nettype none
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module saturn_regs_pc_rstk (
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i_clk,
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i_clk_en,
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i_reset,
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i_phases,
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i_phase,
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i_cycle_ctr,
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i_bus_busy,
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i_alu_busy,
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i_exec_unit_busy,
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i_nibble,
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i_jump_instr,
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i_jump_length,
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i_block_0x,
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i_push_pc,
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i_rtn_instr,
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o_current_pc,
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o_reload_pc,
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/* debugger access */
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i_dbg_rstk_ptr,
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o_dbg_rstk_val,
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o_reg_rstk_ptr
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);
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input wire [0:0] i_clk;
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input wire [0:0] i_clk_en;
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input wire [0:0] i_reset;
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input wire [3:0] i_phases;
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input wire [1:0] i_phase;
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input wire [31:0] i_cycle_ctr;
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input wire [0:0] i_bus_busy;
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input wire [0:0] i_alu_busy;
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input wire [0:0] i_exec_unit_busy;
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input wire [3:0] i_nibble;
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input wire [0:0] i_jump_instr;
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input wire [2:0] i_jump_length;
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input wire [0:0] i_block_0x;
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input wire [0:0] i_push_pc;
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input wire [0:0] i_rtn_instr;
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output wire [19:0] o_current_pc;
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output reg [0:0] o_reload_pc;
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input wire [2:0] i_dbg_rstk_ptr;
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output wire [19:0] o_dbg_rstk_val;
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output wire [2:0] o_reg_rstk_ptr;
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assign o_dbg_rstk_val = reg_RSTK[i_dbg_rstk_ptr];
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assign o_reg_rstk_ptr = reg_rstk_ptr;
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/**************************************************************************************************
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*
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* pc and rstk handling module
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*
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*************************************************************************************************/
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wire [0:0] do_jump_instr = !just_reset && i_jump_instr;
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/*
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* local variables
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*/
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reg [0:0] just_reset;
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reg [2:0] init_counter;
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reg [0:0] jump_decode;
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reg [0:0] jump_exec;
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reg [2:0] jump_counter;
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reg [19:0] jump_base;
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reg [19:0] jump_offset;
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wire [0:0] jump_rel2 = i_jump_instr && (i_jump_length == 3'd1);
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wire [0:0] jump_rel3 = i_jump_instr && (i_jump_length == 3'd2);
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wire [0:0] jump_rel4 = i_jump_instr && (i_jump_length == 3'd3);
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wire [0:0] jump_abs5 = i_jump_instr && (i_jump_length == 3'd4);
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wire [0:0] jump_relative = jump_rel2 || jump_rel3 || jump_rel4;
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reg [19:0] jump_next_offset;
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always @(*) begin
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case (jump_counter)
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3'd0: jump_next_offset = { {16{1'b0}}, i_nibble};
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3'd1: jump_next_offset = { {12{jump_rel2?i_nibble[3]:1'b0}} , i_nibble, jump_offset[ 3:0]};
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3'd2: jump_next_offset = { { 8{jump_rel3?i_nibble[3]:1'b0}} , i_nibble, jump_offset[ 7:0]};
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3'd3: jump_next_offset = { { 4{jump_rel4?i_nibble[3]:1'b0}} , i_nibble, jump_offset[11:0]};
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3'd4: jump_next_offset = { i_nibble, jump_offset[15:0]};
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default: jump_next_offset = 20'h00000;
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endcase
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end
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reg [19:0] reg_PC;
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reg [2:0] reg_rstk_ptr;
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reg [19:0] reg_RSTK[0:7];
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assign o_current_pc = reg_PC;
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initial begin
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o_reload_pc = 1'b0;
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just_reset = 1'b1;
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init_counter = 3'd0;
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jump_decode = 1'b0;
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jump_exec = 1'b0;
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jump_counter = 3'd0;
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reg_PC = 20'h00000;
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reg_rstk_ptr = 3'd7;
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end
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/*
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* the process
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*/
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always @(posedge i_clk) begin
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/* initialize RSTK */
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if (just_reset || (init_counter != 0)) begin
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`ifdef SIM
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$display("PC_RSTK %0d: [%d] initializing RSTK[%0d]", i_phase, i_cycle_ctr, init_counter);
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`endif
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reg_RSTK[init_counter] <= 20'h00000;
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init_counter <= init_counter + 3'd1;
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if (init_counter == 3'd7) begin
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`ifdef SIM
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$display("PC_RSTK %0d: [%d] exit from reset mode", i_phase, i_cycle_ctr);
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`endif
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just_reset <= 1'b0;
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end
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end
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/*
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* only do something when nothing is busy doing some other tasks
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* either talking to the bus, or debugging something
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*/
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// if (!i_debug_cycle)
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// $display("PC_RSTK %0d: [%d] !i_bus_busy %b", i_phase, i_cycle_ctr, !i_bus_busy);
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if (i_clk_en && !i_bus_busy && !i_exec_unit_busy) begin
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// if (i_phases[3] && just_reset) begin
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// $display("PC_RSTK %0d: [%d] exit from reset mode", i_phase, i_cycle_ctr);
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// just_reset <= 1'b0;
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// end
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if (i_phases[1] && !just_reset) begin
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$display("PC_RSTK %0d: [%d] inc_pc %5h => %5h", i_phase, i_cycle_ctr, reg_PC, reg_PC + 20'h00001);
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reg_PC <= reg_PC + 20'h00001;
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end
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/*
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* jump instruction calculations
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*/
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/* start the jump instruction
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* the jump base is:
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* address of first nibble of the offset when goto
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* address of nibble after the offset when gosub
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*/
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if (i_phases[3] && do_jump_instr && !jump_decode) begin
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$display("PC_RSTK %0d: [%d] start decode jump %0d | jump_base %5h", i_phase, i_cycle_ctr, i_jump_length, reg_PC);
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jump_counter <= 3'd0;
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jump_base <= reg_PC;
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jump_decode <= 1'b1;
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end
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/* one step of the calculation (one nibble of data came in) */
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if (i_phases[2] && do_jump_instr && jump_decode) begin
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$display("PC_RSTK %0d: [%d] decode jump %0d/%0d %h %5h", i_phase, i_cycle_ctr, i_jump_length, jump_counter, i_nibble, jump_next_offset);
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jump_offset <= jump_next_offset;
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jump_counter <= jump_counter + 3'd1;
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if (jump_counter == i_jump_length) begin
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$write("PC_RSTK %0d: [%d] execute jump(%0d) jump_base %h jump_next_offset %h", i_phase, i_cycle_ctr, i_jump_length, jump_base, jump_next_offset);
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jump_decode <= 1'b0;
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// jump_exec <= 1'b1;
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// o_reload_pc <= 1'b1;
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reg_PC <= jump_relative ? jump_next_offset + jump_base : jump_next_offset;
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if (i_push_pc) begin
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$write(" ( push %5h => RSTK[%0d] )", reg_PC, reg_rstk_ptr + 3'd1);
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reg_RSTK[(reg_rstk_ptr + 3'o1)&3'o7] <= reg_PC;
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reg_rstk_ptr <= reg_rstk_ptr + 3'd1;
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end
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$write("\n");
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end
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end
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// /* all done, apply to PC and RSTK */
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// if (i_phases[3] && do_jump_instr && jump_exec) begin
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// $write("PC_RSTK %0d: [%d] execute jump %0d", i_phase, i_cycle_ctr, i_jump_length);
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// if (i_push_pc) begin
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// $write(" ( push %5h => RSTK[%0d])", reg_PC, reg_rstk_ptr + 3'd1);
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// reg_RSTK[(reg_rstk_ptr + 3'o1)&3'o7] <= reg_PC;
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// reg_rstk_ptr <= reg_rstk_ptr + 3'd1;
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// end
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// $display("");
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// reg_PC <= jump_relative ? jump_offset + jump_base : jump_offset;
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// jump_exec <= 1'b0;
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// o_reload_pc <= 1'b0;
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// end
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/*
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* RTN instruction
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*/
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/* this happens at the same time in the decoder */
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if (i_phases[2] && i_block_0x && (i_nibble[3:2] == 2'b00)) begin
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/* this is an RTN */
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$write("PC_RSTK %0d: [%d] RTN", i_phase, i_cycle_ctr);
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case (i_nibble)
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4'h0: $display("SXM");
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4'h2: $display("SC");
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4'h3: $display("CC");
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default: begin end
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endcase
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// o_reload_pc <= 1'b1;
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end
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if (i_phases[3] && i_rtn_instr) begin
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$display("PC_RSTK %0d: [%d] execute RTN back to %5h", i_phase, i_cycle_ctr, reg_RSTK[reg_rstk_ptr]);
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reg_PC <= reg_RSTK[reg_rstk_ptr];
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reg_RSTK[reg_rstk_ptr] <= 20'h00000;
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reg_rstk_ptr <= (reg_rstk_ptr - 3'd1) & 3'd7;
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/* o_reload_pc was set in advance above */
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// o_reload_pc <= 1'b0;
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end
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end
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// if (i_phases[0] && i_clk_en) begin
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// $write("RSTK : ptr %0d | ", reg_rstk_ptr);
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// for (tmp_ctr = 4'd0; tmp_ctr < 4'd8; tmp_ctr = tmp_ctr + 4'd1)
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// $write("%0d => %5h | ", tmp_ctr, reg_RSTK[tmp_ctr]);
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// $write("\n");
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// end
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if (i_reset) begin
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o_reload_pc <= 1'b0;
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just_reset <= 1'b1;
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init_counter <= 3'd0;
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jump_decode <= 1'b0;
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jump_exec <= 1'b0;
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jump_counter <= 3'd0;
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reg_PC <= 20'h00000;
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reg_rstk_ptr <= 3'd7;
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end
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end
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reg [3:0] tmp_ctr;
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endmodule |