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28 lines
714 B
Verilog
28 lines
714 B
Verilog
/******************************************************************************
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* 8
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* a lot of things start with 8...
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*
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*/
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`include "decstates.v"
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`DEC_8X: begin
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case (nb_in)
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4'h0: decstate <= `DEC_80X;
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4'h2: decstate <= `DEC_82X_CLRHST;
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4'h4: decstate <= `DEC_ST_EQ_0_N;
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4'h5: decstate <= `DEC_ST_EQ_1_N;
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4'h6: decstate <= `DEC_TEST_ST_EQ_0_N;
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4'h7: decstate <= `DEC_TEST_ST_EQ_1_N;
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4'h8: decstate <= `DEC_TEST_P_NEQ_N;
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4'h9: decstate <= `DEC_TEST_P_EQ_N;
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4'hA: decstate <= `DEC_8AX;
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4'hD: decstate <= `DEC_GOVLNG;
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4'hF: decstate <= `DEC_GOSBVL;
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default: begin
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$display("ERROR : DEC_8X");
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decode_error <= 1;
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end
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endcase
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end
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