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15 lines
280 B
Verilog
15 lines
280 B
Verilog
/******************************************************************************
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* 80Cn C=P n
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*
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*
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*/
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`include "decstates.v"
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`DEC_C_EQ_P_N: begin
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C[nibble*4+:4] <= P;
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decstate <= `DEC_START;
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`ifdef SIM
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$display("%05h C=P\t%h", inst_start_PC, nibble);
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`endif
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end
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