mirror of
https://github.com/sxpert/hp-saturn
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21 lines
436 B
Verilog
21 lines
436 B
Verilog
/******************************************************************************
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* 84n ST=0 n
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* 85n ST=1 n
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*/
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`include "decstates.v"
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`DEC_ST_EQ_0_N: begin
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ST[nibble] <= 0;
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decstate <= `DEC_START;
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`ifdef SIM
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$display("%05h ST=0\t%h", inst_start_PC, nibble);
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`endif
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end
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`DEC_ST_EQ_1_N: begin
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ST[nibble] <= 1;
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decstate <= `DEC_START;
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`ifdef SIM
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$display("%05h ST=1\t%h", inst_start_PC, nibble);
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`endif
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end
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