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https://github.com/sxpert/hp-saturn
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18 lines
No EOL
634 B
Verilog
18 lines
No EOL
634 B
Verilog
`DEC_AC_BIT_SET_TEST: begin
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$display("ERROR: %h | t_reg %b | t_set_test %b | t_set_test_val %b",
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nb_in, t_reg, t_set_test, t_set_test_val);
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if (!t_set_test) begin
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if (!t_reg) A[nb_in] <= t_set_test_val;
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else C[nb_in] <= t_set_test_val;
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decstate <= `DEC_START;
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end else begin
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if (!t_reg) Carry <= (A[nb_in] == t_set_test_val);
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else Carry <= (C[nb_in] == t_set_test_val);
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decstate <= `DEC_TEST_GO;
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end
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`ifdef SIM
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$display("%5h %s%sBIT=%b\t%h",
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inst_start_PC, t_set_test?"?":"",
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t_reg?"C":"A", t_set_test_val, nb_in);
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`endif
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end |