mirror of
https://github.com/sxpert/hp-saturn
synced 2024-11-16 19:50:19 +01:00
148 lines
2.6 KiB
Verilog
148 lines
2.6 KiB
Verilog
`define MMIO
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`define SYSRAM
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`include "bus_commands.v"
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`ifdef MMIO
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`include "hp48_01_io_ram.v"
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`endif
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`ifdef SYSRAM
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`include "hp48_02_sys_ram.v"
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`endif
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`include "hp48_06_rom.v"
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`ifndef _HP48_BUS
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`define _HP48_BUS
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/**************************************************************************************************
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*
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* Bus manager
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*
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*
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*
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*/
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module hp48_bus (
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input strobe,
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input reset,
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input [19:0] address,
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input [3:0] command,
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input [3:0] nibble_in,
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output [3:0] nibble_out,
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output bus_error
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);
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// mmio
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wire [3:0] mmio_nibble_in;
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wire [3:0] mmio_nibble_out;
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wire mmio_active;
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wire mmio_daisy_in;
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wire mmio_daisy_out;
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wire mmio_error;
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// sysram
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wire [3:0] sysram_nibble_in;
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wire [3:0] sysram_nibble_out;
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wire sysram_active;
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wire sysram_daisy_in;
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wire sysram_daisy_out;
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wire sysram_error;
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// rom
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wire [3:0] rom_nibble_out;
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`ifdef MMIO
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//
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// listed in order of priority
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//
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hp48_io_ram dev_io_ram (
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.strobe (strobe),
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.reset (reset),
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.address (address),
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.command (command),
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.nibble_in (mmio_nibble_in),
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.nibble_out (mmio_nibble_out),
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.active (mmio_active),
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.daisy_in (mmio_daisy_in),
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.daisy_out (mmio_daisy_out),
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.error (mmio_error)
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);
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assign mmio_nibble_in = nibble_in;
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assign mmio_daisy_in = 1;
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`else
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assign mmio_error = 0;
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assign mmio_active = 0;
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assign mmio_nibble_out = 0;
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assign mmio_error = 0;
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`endif
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`ifdef SYSRAM
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hp48_sys_ram dev_sys_ram (
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.strobe (strobe),
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.reset (reset),
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.address (address),
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.command (command),
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.nibble_in (sysram_nibble_in),
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.nibble_out (sysram_nibble_out),
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.active (sysram_active),
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.daisy_in (sysram_daisy_in),
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.daisy_out (sysram_daisy_out),
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.error (sysram_error)
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);
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assign sysram_nibble_in = nibble_in;
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assign sysram_daisy_in = mmio_daisy_out;
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`else
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assign sysram_active = 0;
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assign sysram_nibble_out = 0;
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assign sysram_error = 0;
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`endif
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hp48_rom dev_rom (
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.strobe (strobe),
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.address (address),
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.command (command),
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.nibble_out (rom_nibble_out)
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);
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assign bus_error = mmio_error | sysram_error;
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wire show_mmio;
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wire show_sysram;
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wire show_rom;
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assign show_mmio = mmio_active;
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assign show_sysram = !mmio_active & sysram_active;
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assign show_rom = !mmio_active & !sysram_active;
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assign nibble_out = {4 {strobe}} & (
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({4 {show_mmio}} & mmio_nibble_out) |
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({4 {show_sysram}} & sysram_nibble_out) |
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({4 {show_rom}} & rom_nibble_out));
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// initial begin
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// $monitor("BUS > STRB %b | MMIO %b %h | SYSRAM %b %h | ROM %b %h | IN %h | OUT %h",
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// strobe,
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// show_mmio, mmio_nibble_out,
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// show_sysram, sysram_nibble_out,
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// show_rom, rom_nibble_out,
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// nibble_in, nibble_out);
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// end
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endmodule
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`endif
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