mirror of
https://github.com/sxpert/hp-saturn
synced 2024-12-27 09:58:16 +01:00
42 lines
No EOL
1.2 KiB
Verilog
42 lines
No EOL
1.2 KiB
Verilog
/******************************************************************************
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* xx
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* RTNYES or GOYES
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*
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*/
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`include "decstates.v"
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`DEC_TEST_GO: begin
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jump_base <= PC;
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jump_offset <= {{16{1'b0}},nb_in};
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decstate <= `DEC_TEST_GO_1;
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end
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`DEC_TEST_GO_1: begin
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$display("DEC_TEST_GO_1 opcode %h | base %h | offset %h",
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{nb_in, jump_offset[3:0]}, jump_base,
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{{12{nb_in[3]}},nb_in,jump_offset[3:0]});
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if (Carry) begin
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case ({nb_in, jump_offset[3:0]})
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8'h00: begin // RTNYES
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new_PC <= RSTK[rstk_ptr];
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RSTK[rstk_ptr] <= 0;
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rstk_ptr <= rstk_ptr - 1;
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next_cycle <= `BUSCMD_LOAD_PC;
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end
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default: begin // GOYES
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new_PC <= jump_base + {{12{nb_in[3]}},nb_in,jump_offset[3:0]};
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next_cycle <= `BUSCMD_LOAD_PC;
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end
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endcase
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end
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`ifdef SIM
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$write("%5h ", jump_base);
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case ({nb_in, jump_offset[3:0]})
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8'h00: $display("RTNYES");
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default: $display ("GOYES\t%2h\t=> %5h", {nb_in, jump_offset[3:0]},
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jump_base + {{12{nb_in[3]}},nb_in,jump_offset[3:0]});
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endcase
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`endif
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decstate <= `DEC_START;
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end |