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https://github.com/sxpert/hp-saturn
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27 lines
551 B
Verilog
27 lines
551 B
Verilog
/******************************************************************************
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* Dx
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* register manipulation field A
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*
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*/
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`include "decstates.v"
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`DEC_DX: begin
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case (nb_in)
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4'hA: begin
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A[19:0] <= C[19:0];
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$display("%5h A=C\tA", inst_start_PC);
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end
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4'hE: begin
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A[19:0] <= C[19:0];
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C[19:0] <= A[19:0];
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$display("%5h ACEX\tA", inst_start_PC);
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end
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default: begin
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$display("ERROR : DEC_DX");
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decode_error <= 1;
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end
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endcase
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decstate <= `DEC_START;
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end
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