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https://github.com/sxpert/hp-saturn
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22 lines
442 B
Verilog
22 lines
442 B
Verilog
/******************************************************************************
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* 8Ax
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* a lot of things start with 8...
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*
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*/
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`include "decstates.v"
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`DEC_8AX: begin
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case (nb_in)
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4'h6: begin
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Carry = !(A[19:0] == C[19:0]);
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$display("%5h ?A#C\tA", inst_start_PC);
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end
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default: begin
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$display("ERROR : DEC_8AX");
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decode_error <= 1;
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end
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endcase
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decstate <= `DEC_TEST_GO;
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end
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