mirror of
https://github.com/sxpert/hp-saturn
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20 lines
No EOL
441 B
Verilog
20 lines
No EOL
441 B
Verilog
/******************************************************************************
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* 88n ?P# n
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* 89n ?P= n
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*
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*/
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`DEC_TEST_P_NEQ_N: begin
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Carry <= !(P == nb_in);
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decstate <= `DEC_TEST_GO;
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`ifdef SIM
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$display("%5h ?P#\t\t%h", inst_start_PC, nb_in);
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`endif
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end
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`DEC_TEST_P_EQ_N: begin
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Carry <= (P == nb_in);
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decstate <= `DEC_TEST_GO;
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`ifdef SIM
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$display("%5h ?P=\t\t%h", inst_start_PC, nb_in);
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`endif
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end |